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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
drivers
/
cxl
/
pci.c
Age
Commit message (
Expand
)
Author
Files
Lines
2023-02-15
Merge branch 'for-6.3/cxl' into cxl/next
Dan Williams
1
-8
/
+62
2023-02-15
cxl: add RAS status unmasking for CXL
Dave Jiang
1
-0
/
+65
2023-02-15
cxl: remove unnecessary calling of pci_enable_pcie_error_reporting()
Dave Jiang
1
-11
/
+0
2023-01-31
cxl/pci: Fix irq oneshot expectations
Dan Williams
1
-1
/
+2
2023-01-30
cxl/pci: Set the device timestamp
Jonathan Cameron
1
-0
/
+4
2023-01-27
cxl/mem: Wire up event interrupts
Davidlohr Bueso
1
-10
/
+211
2023-01-27
cxl/mem: Read, trace, and clear events on driver load
Ira Weiny
1
-0
/
+33
2023-01-25
cxl/pci: Show opcode in debug messages when sending a command
Robert Richter
1
-1
/
+1
2023-01-05
cxl/pci: Move tracepoint definitions to drivers/cxl/core/
Dan Williams
1
-111
/
+0
2022-12-07
cxl/pci: Remove endian confusion
Dan Williams
1
-4
/
+3
2022-12-07
cxl/pci: Add some type-safety to the AER trace points
Dan Williams
1
-2
/
+2
2022-12-05
Merge branch 'for-6.2/cxl-aer' into for-6.2/cxl
Dan Williams
1
-40
/
+173
2022-12-05
cxl/port: Add RCD endpoint port enumeration
Dan Williams
1
-0
/
+10
2022-12-04
cxl/pci: Add callback to log AER correctable error
Dave Jiang
1
-0
/
+20
2022-12-04
cxl/pci: Add (hopeful) error handling support
Dan Williams
1
-0
/
+137
2022-12-04
cxl/pci: add tracepoint events for CXL RAS
Dave Jiang
1
-0
/
+2
2022-12-04
cxl/pci: Find and map the RAS Capability Structure
Dan Williams
1
-0
/
+8
2022-12-04
cxl/core/regs: Make cxl_map_{component, device}_regs() device generic
Dan Williams
1
-19
/
+6
2022-12-04
cxl/pci: Kill cxl_map_regs()
Dan Williams
1
-22
/
+1
2022-12-03
cxl/pmem: Refactor nvdimm device registration, delete the workqueue
Dan Williams
1
-3
/
+0
2022-11-14
cxl/doe: Request exclusive DOE access
Ira Weiny
1
-0
/
+5
2022-07-20
cxl/pci: Create PCI DOE mailbox's for memory devices
Ira Weiny
1
-0
/
+44
2022-07-10
cxl/mem: Convert partition-info to resources
Dan Williams
1
-1
/
+1
2022-05-19
cxl/mem: Consolidate CXL DVSEC Range enumeration in the core
Dan Williams
1
-135
/
+0
2022-05-19
cxl/pci: Move cxl_await_media_ready() to the core
Dan Williams
1
-44
/
+1
2022-05-19
cxl/pci: Drop wait_for_valid() from cxl_await_media_ready()
Dan Williams
1
-4
/
+0
2022-05-19
cxl/pci: Consolidate wait_for_media() and wait_for_media_ready()
Dan Williams
1
-2
/
+2
2022-04-13
cxl/pci: Make cxl_dvsec_ranges() failure not fatal to cxl_pci
Dan Williams
1
-9
/
+18
2022-04-13
cxl/pci: Add debug for DVSEC range init failures
Dan Williams
1
-3
/
+10
2022-04-13
cxl/mbox: Use new return_code handling
Davidlohr Bueso
1
-1
/
+2
2022-04-13
cxl/mbox: Improve handling of mbox_cmd hw return codes
Davidlohr Bueso
1
-1
/
+1
2022-04-13
cxl/pci: Use CXL_MBOX_SUCCESS to check against mbox_cmd return code
Davidlohr Bueso
1
-2
/
+2
2022-04-08
cxl/pci: Drop shadowed variable
Dan Williams
1
-1
/
+0
2022-02-09
cxl/pci: Emit device serial number
Dan Williams
1
-0
/
+1
2022-02-09
cxl/pci: Implement wait for media active
Ben Widawsky
1
-1
/
+48
2022-02-09
cxl/pci: Retrieve CXL DVSEC memory info
Ben Widawsky
1
-0
/
+119
2022-02-09
cxl/pci: Cache device DVSEC offset
Ben Widawsky
1
-0
/
+6
2022-02-09
cxl/pci: Store component register base in cxlds
Ben Widawsky
1
-0
/
+11
2022-02-09
cxl/pci: Rename pci.h to cxlpci.h
Dan Williams
1
-1
/
+1
2022-02-09
cxl/acpi: Map component registers for Root Ports
Ben Widawsky
1
-52
/
+0
2022-02-09
cxl: Flesh out register names
Ben Widawsky
1
-7
/
+7
2022-02-09
cxl/pci: Defer mailbox status checks to command timeouts
Dan Williams
1
-101
/
+33
2022-02-09
cxl/pci: Implement Interface Ready Timeout
Ben Widawsky
1
-0
/
+35
2021-11-15
cxl/memdev: Change cxl_mem to a more descriptive name
Ira Weiny
1
-60
/
+60
2021-10-29
cxl/pci: Use pci core's DVSEC functionality
Ben Widawsky
1
-24
/
+2
2021-10-29
cxl/pci: Split cxl_pci_setup_regs()
Ben Widawsky
1
-36
/
+37
2021-10-29
cxl/pci: Add @base to cxl_register_map
Dan Williams
1
-15
/
+16
2021-10-29
cxl/pci: Make more use of cxl_register_map
Ben Widawsky
1
-34
/
+25
2021-10-29
cxl/pci: Remove pci request/release regions
Ben Widawsky
1
-5
/
+0
2021-10-29
cxl/pci: Fix NULL vs ERR_PTR confusion
Dan Williams
1
-1
/
+1
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