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path: root/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
AgeCommit message (Expand)AuthorFilesLines
2023-10-20drm/amd/display: Remove brackets in macro to conform to coding styleStylon Wang1-118/+36
2023-09-12drm/amd/display: Add DCHUBBUB callback to report MALL statusAurabindo Pillai1-0/+1
2023-08-30drm/amd/display: Update DCN32 for DCN35 supportQingqing Zhuo1-2/+0
2023-08-30drm/amd/display: add new resource interface for acquiring sec opp heads and r...Wenjing Liu1-0/+10
2023-08-30drm/amd/display: Add support for 1080p SubVP to reduce idle powerEthan Bitnun1-1/+1
2023-08-08drm/amd/display: rename acquire_idle_pipe_for_layer to acquire_free_pipe_as_s...Wenjing Liu1-1/+1
2023-08-08drm/amd/display: update add plane to context logic with a new algorithmWenjing Liu1-4/+4
2023-06-15drm/amd/display: SubVP high refresh only if all displays >= 120hzAlvin Lee1-0/+4
2023-06-09drm/amd/display: Only use ODM2:1 policy for high pixel rate displaysAurabindo Pillai1-0/+1
2023-06-09Revert "drm/amd/display: Only use ODM2:1 policy for high pixel rate displays"Aurabindo Pillai1-1/+0
2023-06-09drm/amd/display: Update vactive margin and max vblank for fpo + vactiveAlvin Lee1-1/+0
2023-06-09drm/amd/display: Block SubVP on displays that have pixclk > 1800MhzAlvin Lee1-0/+1
2023-04-25drm/amd/display: Enable SubVP for high refresh rate displaysAlvin Lee1-0/+14
2023-04-12drm/amd/display: Add FPO + VActive supportAlvin Lee1-0/+3
2023-04-12drm/amd/display: add scaler control for dcn32Zhikai Zhai1-0/+1
2023-03-22drm/amd/display: Implement workaround for writing to OTG_PIXEL_RATE_DIV registerSaaem Rizvi1-1/+2
2023-02-14drm/amd/display: Set max vratio for prefetch to 7.9 for YUV420 MPOAlvin Lee1-0/+2
2023-01-24drm/amd/display: adjust MALL size available for DCN32 and DCN321Samson Tam1-0/+2
2023-01-24drm/amd/display: Set init freq for DCFCLK DSAlvin Lee1-0/+1
2023-01-24drm/amd/display: Disable SubVP for PSR panelsAlvin Lee1-0/+1
2023-01-17drm/amd/display: Allow subvp on vactive pipes that are 2560x1440@60Alvin Lee1-0/+2
2023-01-17drm/amd/display: Use DML for MALL SS and Subvp allocation calculationsDillon Varone1-2/+11
2022-12-15drm/amd/display: Block subvp if center timing is in useAlvin Lee1-0/+1
2022-11-29drm/amd/display: Retain phantom pipes when min transition into subvp (#7358)Alvin Lee1-11/+0
2022-11-29drm/amd/display: Don't overwrite subvp pipe info in fast updatesAlvin Lee1-1/+1
2022-11-23drm/amd/display: Retain phantom plane/stream if validation failsAlvin Lee1-0/+3
2022-11-15drm/amd/display: enable dchub request limit for DCN 3.2.xJun Lei1-1/+2
2022-10-06drm/amd/display: For SubVP pipe split case use min transition into MPOAlvin Lee1-0/+20
2022-10-06drm/amd/display: Block SubVP if rotation being usedAlvin Lee1-0/+2
2022-09-29drm/amd/display: Only use ODM2:1 policy for high pixel rate displaysAlvin Lee1-0/+1
2022-09-19drm/amd/display: Do second pass through DML for DET calculationAlvin Lee1-2/+7
2022-09-19drm/amd/display: Fix pipe split predictionAlvin Lee1-2/+4
2022-09-13drm/amd/display: Fix register definitions for DCN32/321Aurabindo Pillai1-70/+146
2022-09-13drm/amd/display: Update MBLK calculation for SubVPAlvin Lee1-0/+3
2022-09-13drm/amd/display: Correct I2C register offsetChris Park1-8/+9
2022-08-25drm/amd/display: change to runtime initialization for reg offsets for DCN32Aurabindo Pillai1-0/+1080
2022-07-26drm/amd/display: Calculate MALL cache lines based on Mblks requiredAlvin Lee1-0/+1
2022-07-26drm/amd/display: Fix two MPO videos in single display ODM combine modeSamson Tam1-0/+6
2022-07-25drm/amd/display: Move dlg params calculationRodrigo Siqueira1-6/+0
2022-07-25drm/amd/display: Move SubVP functions to dcn32_fpuRodrigo Siqueira1-0/+2
2022-07-25drm/amd/display: Move insert entry table to the FPU codeRodrigo Siqueira1-0/+3
2022-07-25drm/amd/display: Move predict pipe to dml fpu folderRodrigo Siqueira1-2/+0
2022-07-25drm/amd/display: Update de-tile override to anticipate pipe splittingTaimur Hassan1-2/+4
2022-07-05drm/amd/display: Add SubVP required codeAlvin Lee1-1/+19
2022-06-03drm/amd/display: add DCN32/321 specific files for Display CoreAurabindo Pillai1-0/+88
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