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path: root/drivers/gpu/drm/i915/display/intel_cx0_phy.c
AgeCommit message (Expand)AuthorFilesLines
2024-02-14drm/i915/display: update pll values in sync with Bspec for MTLRavi Kumar Vodapalli1-16/+16
2024-01-30drm/i915/xe2lpd: Move registers to PICALucas De Marchi1-42/+45
2024-01-08drm/i915/display: Use helper to select C20 MPLLA/BMika Kahola1-6/+11
2024-01-04drm/i915/display: Skip C10 state verification in case of fastsetMika Kahola1-0/+3
2024-01-04drm/i915/display: Cleanup mplla/mpllb selectionMika Kahola1-24/+15
2024-01-04drm/i915/display: Store hw clock for C20Mika Kahola1-45/+52
2024-01-04drm/i915/display: Fix C20 pll selection for state verificationMika Kahola1-10/+15
2023-12-15drm/i915/mtl: Fix HDMI/DP PLL clock selectionImre Deak1-1/+2
2023-12-08drm/i915/mtl: Rename the link_bit_rate to clock in C20 pll_stateRadhakrishna Sripada1-21/+21
2023-12-08drm/i915/mtl: Remove misleading "clock" field from C20 pll_stateRadhakrishna Sripada1-18/+0
2023-12-08drm/i915/mtl: Use port clock compatible numbers for C20 phyRadhakrishna Sripada1-21/+22
2023-12-01drm/i915/display: Skip state verification with TBT-ALT modeMika Kahola1-1/+10
2023-11-13drm/i915/mtl: C20 state verificationMika Kahola1-34/+86
2023-10-30drm/i915/display: Abstract C10/C20 pll calculationLucas De Marchi1-4/+16
2023-10-30drm/i915/display: Abstract C10/C20 pll hw readoutLucas De Marchi1-4/+16
2023-10-30drm/i915/lnl: Extend C10/C20 phyLucas De Marchi1-1/+1
2023-10-26drm/i915/display: Reset message bus after each read/write operationMika Kahola1-0/+14
2023-10-16drm/i915/display: Clean up zero initializersVille Syrjälä1-1/+1
2023-10-11drm/i915/cx0: Only clear/set the Pipe Reset bit of the PHY Lanes OwnedKhaled Almahallawy1-2/+1
2023-10-07drm/i915: Simplify snps/c10x DPLL state checker calling convetionVille Syrjälä1-2/+3
2023-10-07drm/i915: Constify the snps/c10x PLL state checkersVille Syrjälä1-2/+2
2023-09-18drm/i915/cx0: Add step for programming msgbus timerGustavo Sousa1-47/+40
2023-09-06drm/i915/cx0: Check and increase msgbus timeout thresholdGustavo Sousa1-0/+39
2023-09-06drm/i915/tc: remove "fia" from intel_tc_port_fia_max_lane_count()Luca Coelho1-1/+1
2023-08-22drm/i915/display: Eliminate IS_METEORLAKE checksMatt Roper1-1/+1
2023-08-17drm/i915/cx0: Program vswing only for owned lanesGustavo Sousa1-11/+14
2023-08-17drm/i915/cx0: Enable/disable TX only for owned PHY lanesGustavo Sousa1-3/+6
2023-08-17drm/i915: Simplify intel_cx0_program_phy_lane() with loopGustavo Sousa1-59/+20
2023-08-17drm/i915/cx0: Add intel_cx0_get_owned_lane_mask()Gustavo Sousa1-17/+27
2023-06-21drm/i915/mtl: Fix SSC selection for MPLLARadhakrishna Sripada1-1/+2
2023-06-15drm/i915/mtl: Cleanup usage of phy lane resetMika Kahola1-7/+6
2023-06-05drm/i915/mtl: Reset only one lane in case of MFDMika Kahola1-16/+23
2023-05-19drm/i915/hdmi: C20 computed PLL frequenciesClint Taylor1-6/+84
2023-05-18drm/i915/mtl: Fix expected reg value for Thunderbolt PLL disablingMika Kahola1-3/+1
2023-05-15drm/i915/display: add i915 parameter to I915_STATE_WARN()Jani Nikula1-5/+5
2023-04-29drm/i915/mtl: Power up TCSSMika Kahola1-0/+19
2023-04-29drm/i915/mtl: Readout Thunderbolt HW stateMika Kahola1-0/+27
2023-04-29drm/i915/mtl: Enabling/disabling sequence Thunderbolt pllMika Kahola1-3/+132
2023-04-29drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLAMika Kahola1-2/+5
2023-04-29drm/i915/mtl: C20 port clock calculationMika Kahola1-0/+45
2023-04-29drm/i915/mtl: Dump C20 pll hw stateMika Kahola1-0/+20
2023-04-29drm/i915/mtl: C20 HW readoutMika Kahola1-12/+612
2023-04-29drm/i915/mtl: C20 PLL programmingMika Kahola1-38/+250
2023-04-15drm/i915: Make intel_{mpllb,c10pll}_state_verify() saferVille Syrjälä1-0/+5
2023-04-14drm/i915/mtl: Add C10 phy programming for HDMIRadhakrishna Sripada1-3/+607
2023-04-14drm/i915/mtl: Add vswing programming for C10 physMika Kahola1-5/+97
2023-04-14drm/i915/mtl: Add Support for C10 PHY message bus and pll programmingRadhakrishna Sripada1-0/+1207
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