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path: root/drivers/gpu/drm/i915/display
AgeCommit message (Expand)AuthorFilesLines
2021-04-08drm/i915: Fix invalid access to ACPI _DSM objectsTakashi Iwai1-2/+20
2021-03-23drm/i915/dsc: fix DSS CTL register usage for ICL DSI transcodersJani Nikula1-8/+2
2021-03-23drm/i915: Fix enabled_planes bitmaskVille Syrjälä1-2/+3
2021-03-23drm/i915: Disable LTTPR support when the LTTPR rev < 1.4Imre Deak1-4/+10
2021-03-23drm/i915: Disable LTTPR support when the DPCD rev < 1.4Imre Deak3-15/+39
2021-03-23drm/i915/ilk-glk: Fix link training on links with LTTPRsImre Deak2-3/+19
2021-02-25Merge tag 'drm-next-2021-02-26' of git://anongit.freedesktop.org/drm/drmLinus Torvalds3-4/+1
2021-02-23drm/i915: Nuke INTEL_OUTPUT_FORMAT_INVALIDVille Syrjälä3-4/+1
2021-02-22Merge tag 'drm-next-2021-02-19' of git://anongit.freedesktop.org/drm/drmLinus Torvalds60-7087/+10200
2021-02-17drm/i915: Disallow plane x+w>stride on ilk+ with X-tilingVille Syrjälä3-6/+39
2021-02-10drm/i915: Fix overlay frontbuffer trackingVille Syrjälä1-9/+8
2021-02-09drm/i915/tgl+: Make sure TypeC FIA is powered up when initializing itImre Deak1-30/+37
2021-02-09drm/i915: Reject 446-480MHz HDMI clock on GLKVille Syrjälä1-1/+5
2021-02-04Merge tag 'drm-intel-next-2021-01-29' of git://anongit.freedesktop.org/drm/dr...Dave Airlie8-179/+282
2021-02-02drm/i915/dp: Fix LTTPR vswing/pre-emp setting in non-transparent modeImre Deak3-10/+14
2021-02-02drm/i915/dp: Move intel_dp_set_signal_levels() to intel_dp_link_training.cImre Deak4-21/+20
2021-02-02drm/i915: Fix the MST PBN divider calculationImre Deak1-1/+3
2021-02-02drm/i915/gem: Drop lru bumping on display unpinningChris Wilson2-7/+4
2021-02-02drm/i915/display: Prevent double YUV range correction on HDR planesAndres Calderon Jaramillo2-55/+12
2021-02-02drm/i915: Power up combo PHY lanes for for HDMI as wellVille Syrjälä1-0/+2
2021-02-02drm/i915: Extract intel_ddi_power_up_lanes()Ville Syrjälä1-16/+19
2021-02-02drm/i915: Skip vswing programming for TBTVille Syrjälä1-0/+6
2021-01-29drm/i915/dp: Prevent setting the LTTPR LT mode if no LTTPRs are detectedImre Deak1-21/+15
2021-01-29drm/i915: Implement async flips for vlv/chvVille Syrjälä2-6/+47
2021-01-29drm/i915: Implement async flip for ilk/snbVille Syrjälä2-1/+26
2021-01-29drm/i915: Implement async flip for ivb/hswVille Syrjälä2-1/+26
2021-01-29drm/i915: Implement async flips for bdwVille Syrjälä2-3/+58
2021-01-29drm/i915: Limit plane stride to below TILEOFF.x limitVille Syrjälä3-16/+83
2021-01-29drm/i915/gen11+: Only load DRAM information from pcodeJosé Roberto de Souza1-72/+8
2021-01-29Merge tag 'drm-intel-next-2021-01-27' of git://anongit.freedesktop.org/drm/dr...Dave Airlie37-5035/+6372
2021-01-28drm/i915: Fix the MST PBN divider calculationImre Deak1-1/+3
2021-01-28drm/i915/hdcp: Disable the QSES check for HDCP 1.4 over MSTSean Paul1-11/+1
2021-01-28drm/i915/display: Prevent double YUV range correction on HDR planesAndres Calderon Jaramillo2-55/+12
2021-01-28drm/i915: WARN if plane src coords are too bigVille Syrjälä2-0/+11
2021-01-27drm/i915/display/vrr: Skip the VRR HW state readout on DSI transcoderManasi Navare1-1/+1
2021-01-26drm/i915: Fix ICL MG PHY vswing handlingVille Syrjälä1-4/+3
2021-01-26drm/i915: Do a bit more initial readout for dbufVille Syrjälä1-4/+0
2021-01-26drm/i915: Encapsulate dbuf state handling harderVille Syrjälä2-16/+0
2021-01-26drm/i915: Fix vblank evasion with vrrVille Syrjälä1-1/+4
2021-01-26drm/i915: Fix vblank timestamps with VRRVille Syrjälä3-5/+20
2021-01-26drm/i915: Add vrr state dumpVille Syrjälä1-0/+7
2021-01-26drm/i915/display: Helpers for VRR vblank min and max startVille Syrjälä2-0/+38
2021-01-26drm/i915/display: Add HW state readout for VRRManasi Navare3-0/+26
2021-01-26drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP SinkManasi Navare2-1/+20
2021-01-26drm/i915/display/vrr: Disable VRR in modeset disable pathManasi Navare3-0/+16
2021-01-26drm/i915/display/vrr: Send VRR push to flip the frameManasi Navare3-0/+18
2021-01-26drm/i915/display/vrr: Configure and enable VRR in modeset enableManasi Navare3-0/+28
2021-01-26drm/i915/display: VRR + DRRS cannot be enabled togetherVille Syrjälä1-0/+3
2021-01-26drm/i915/display/dp: Do not enable PSR if VRR is enabledManasi Navare1-0/+7
2021-01-26drm/i915/display/dp: Compute VRR state in atomic_checkManasi Navare5-0/+95
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-28 13:17:56 +0300