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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)AuthorFilesLines
2012-12-17drm/i915: Implement WaSetupGtModeTdRowDispatchDaniel Vetter1-1/+2
2012-12-17drm/i915: Implement WaDisableHiZPlanesWhenMSAAEnabledDaniel Vetter1-0/+1
2012-12-10drm/i915: set the LPT FDI RX polarity reversal bit when neededPaulo Zanoni1-0/+1
2012-12-10drm/i915: add lpt_init_pch_refclkPaulo Zanoni1-1/+5
2012-12-10drm/i915: add support for mPHY destination on intel_sbi_{read, write}Paulo Zanoni1-0/+4
2012-11-21drm/i915: make the panel fitter work on pipes B and C on IVBPaulo Zanoni1-0/+2
2012-11-21drm/i915: don't intel_crt_init if DDI A has 4 lanesPaulo Zanoni1-0/+1
2012-11-21drm/i915: make DP work on LPT-LP machinesPaulo Zanoni1-0/+1
2012-11-12drm/i915: Move the remaining gtt codeBen Widawsky1-17/+0
2012-11-12drm/i915: flush system agent TLBs on SNBBen Widawsky1-0/+2
2012-11-12drm/i915: Calculate correct stolen size for GEN7+Ben Widawsky1-0/+2
2012-11-12drm/i915: Stop using AGP layer for GEN6+Ben Widawsky1-0/+6
2012-11-12drm/i915: TLB invalidation with MI_FLUSH_DW requires a post-sync op v3Jesse Barnes1-2/+6
2012-11-12drm/i915: implement WaDisablePSDDualDispatchEnable on IVB & VLVJesse Barnes1-0/+5
2012-11-12drm/i915: implement WaDisableVLVClockGating_VBIIssue on VLVJesse Barnes1-0/+2
2012-11-12drm/i915: implement WaDisableDopClockGatingisable on VLV and IVBJesse Barnes1-0/+4
2012-11-12drm/i915: implement WaDisableL3CacheAging on VLVJesse Barnes1-0/+1
2012-11-12drm/i915: fix Haswell FDI link training codePaulo Zanoni1-6/+11
2012-11-12drm/i915: implement WADP0ClockGatingDisableDaniel Vetter1-0/+4
2012-11-12drm/i915: CPT+ pch transcoder workaroundDaniel Vetter1-2/+3
2012-11-12drm/i915: Add SURFLIVE register definitionsVille Syrjälä1-0/+7
2012-11-12drm/i915: Fix display pixel format handlingVille Syrjälä1-5/+12
2012-11-12drm/i915: implement WaDisableRenderCachePipelinedFlushDaniel Vetter1-0/+1
2012-11-12drm/i915: Fix sprite offset on HSWDamien Lespiau1-0/+3
2012-11-12drm/i915: Fix primary plane offset on HSWDamien Lespiau1-0/+3
2012-11-12drm/i915: check fdi B/C lane sharing constraintDaniel Vetter1-2/+3
2012-10-26drm/i915: convert pipe timing definitions to transcoderPaulo Zanoni1-7/+7
2012-10-26drm/i915: convert CPU M/N timings to transcoderPaulo Zanoni1-8/+8
2012-10-26drm/i915: convert PIPE_MSA_MISC to transcoderPaulo Zanoni1-9/+10
2012-10-26drm/i915: convert PIPECONF to use transcoder instead of pipePaulo Zanoni1-1/+1
2012-10-26drm/i915: convert DDI_FUNC_CTL to transcoderPaulo Zanoni1-27/+32
2012-10-26drm/i915: convert PIPE_CLK_SEL to transcoderPaulo Zanoni1-7/+7
2012-10-26drm/i915: add TRANSCODER_EDPPaulo Zanoni1-0/+1
2012-10-23drm/i915: make edp panel power sequence setup more robustDaniel Vetter1-0/+5
2012-10-22Merge tag 'v3.7-rc2' into drm-intel-next-queuedDaniel Vetter1-1/+8
2012-10-19drm/i915: Consolidate ILK_DSPCLK_GATE and PCH_DSPCLK_GATEDamien Lespiau1-15/+7
2012-10-18drm/i915: add basic Haswell DP link train bitsPaulo Zanoni1-0/+4
2012-10-18drm/i915: add intel_ddi_set_pipe_settingsPaulo Zanoni1-0/+10
2012-10-17drm/i915: Document the multi-threaded FORCEWAKE bitsChris Wilson1-0/+2
2012-10-17drm/i915: Allow DRM_ROOT_ONLY|DRM_MASTER to submit privileged batchbuffersChris Wilson1-2/+5
2012-10-16drm/i915: Workaround to bump rc6 voltage to 450Ben Widawsky1-0/+4
2012-10-12drm/i915: Set guardband clipping workaround bit in the right register.Kenneth Graunke1-1/+1
2012-10-12drm/i915: Fix the SCC/SSC typo in the SPLL bits definitionDamien Lespiau1-3/+3
2012-10-10drm/i915: completely rewrite the Haswell PLL handling codePaulo Zanoni1-0/+1
2012-10-10drm/i915: add haswell_set_pipeconfPaulo Zanoni1-0/+1
2012-10-10drm/i915: enable and disable DDI_FUNC_CTL at the right timePaulo Zanoni1-0/+1
2012-10-10drm/i915: rewrite the LCPLL codePaulo Zanoni1-0/+6
2012-10-04drm/i915: implement WaDisableEarlyCull for VLV and IVBJesse Barnes1-0/+1
2012-10-04drm/i915: implement WaForceL3Serialization on VLV and IVBJesse Barnes1-0/+3
2012-10-04drm/i915: Fix GT_MODE default valueBen Widawsky1-0/+3
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