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path: root/drivers/phy/cadence/phy-cadence-sierra.c
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2021-12-27phy: cadence: Sierra: Add support for derived reference clock outputSwapnil Jakhade1-1/+108
2021-12-27phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configurationSwapnil Jakhade1-1/+376
2021-12-27phy: cadence: Sierra: Add support for PHY multilink configurationsSwapnil Jakhade1-8/+190
2021-12-27phy: cadence: Sierra: Fix to get correct parent for mux clocksSwapnil Jakhade1-5/+26
2021-12-27phy: cadence: Sierra: Update single link PCIe register configurationSwapnil Jakhade1-1/+213
2021-12-27phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operationSwapnil Jakhade1-1/+72
2021-12-27phy: cadence: Sierra: Check cmn_ready assertion during PHY power onSwapnil Jakhade1-0/+45
2021-12-27phy: cadence: Sierra: Add PHY PCS common register configurationsSwapnil Jakhade1-0/+38
2021-12-27phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra ...Swapnil Jakhade1-10/+11
2021-12-27phy: cadence: Sierra: Add support to get SSC type from device treeSwapnil Jakhade1-1/+5
2021-12-27phy: cadence: Sierra: Prepare driver to add support for multilink configurationsSwapnil Jakhade1-56/+139
2021-12-27phy: cadence: Sierra: Use of_device_get_match_data() to get driver dataSwapnil Jakhade1-9/+4
2021-05-31phy: cadence: Sierra: Fix error return code in cdns_sierra_phy_probe()Wang Wensheng1-0/+1
2021-03-31phy: cadence: Sierra: Enable pll_cmnlc and pll_cmnlc1 clocksKishon Vijay Abraham I1-3/+37
2021-03-31phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks)Kishon Vijay Abraham I1-3/+264
2021-03-31phy: cadence: Sierra: Add missing clk_disable_unprepare() in .remove callbackKishon Vijay Abraham I1-0/+3
2021-03-31phy: cadence: Sierra: Add array of input clocks in "struct cdns_sierra_phy"Kishon Vijay Abraham I1-10/+15
2021-03-31phy: cadence: Sierra: Explicitly request exclusive reset controlKishon Vijay Abraham I1-2/+2
2021-03-31phy: cadence: Sierra: Move all reset_control_get*() to a separate functionKishon Vijay Abraham I1-11/+25
2021-03-31phy: cadence: Sierra: Move all clk_get_*() to a separate functionKishon Vijay Abraham I1-22/+35
2021-03-31phy: cadence: Sierra: Create PHY only for "phy" or "link" sub-nodesKishon Vijay Abraham I1-0/+4
2021-03-31phy: cadence: Sierra: Fix PHY power_on sequenceKishon Vijay Abraham I1-1/+6
2020-11-16phy: cadence: convert to devm_platform_ioremap_resourceChunfeng Yun1-3/+1
2020-09-16phy: cadence: Sierra: Constify static structsRikard Falkeborn1-12/+12
2020-05-18phy: cadence: sierra: Fix for USB3 U1/U2 stateSanket Parmar1-13/+14
2020-01-14phy: cadence: Sierra: add phy_reset hookRoger Quadros1-0/+10
2020-01-14phy: cadence: Sierra: remove redundant initialization of pointer regmapColin Ian King1-1/+1
2020-01-08phy: cadence: Sierra: Use correct dev pointer in cdns_sierra_phy_remove()Kishon Vijay Abraham I1-1/+1
2020-01-08phy: cadence: Sierra: Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to...Kishon Vijay Abraham I1-0/+21
2020-01-08phy: cadence: Sierra: Change MAX_LANES of Sierra to 16Kishon Vijay Abraham I1-1/+21
2020-01-08phy: cadence: Sierra: Check for PLL lock during PHY power onKishon Vijay Abraham I1-1/+32
2020-01-08phy: cadence: Sierra: Get reset control "array" for each linkKishon Vijay Abraham I1-1/+1
2020-01-08phy: cadence: Sierra: Configure both lane cdb and common cdb registers for ex...Anil Varughese1-96/+254
2020-01-08phy: cadence: Sierra: Modify register macro names to be in sync with Sierra u...Kishon Vijay Abraham I1-83/+84
2020-01-08phy: cadence: Sierra: Make cdns_sierra_phy_init() as phy_opsKishon Vijay Abraham I1-6/+9
2020-01-08phy: cadence: Sierra: Add support for SERDES_16G used in J721E SoCKishon Vijay Abraham I1-0/+14
2020-01-08phy: cadence: Sierra: Use "regmap" for read and write to Sierra registersKishon Vijay Abraham I1-54/+237
2020-01-08phy: cadence: Sierra: Make "phy_clk" and "sierra_apb" optional resourcesKishon Vijay Abraham I1-2/+2
2018-12-12phy: cadence: Add driver for Sierra PHYAlan Douglas1-0/+395