Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2023-06-13 | ASoC: tlv320aic32x4: pll: Remove impossible condition in clk_aic32x4_pll_dete... | Stephen Boyd | 1 | -5/+1 |
2023-06-09 | ASoC: tlv320aic32x4: div: Switch to determine_rate | Maxime Ripard | 1 | -6/+7 |
2023-06-09 | ASoC: tlv320aic32x4: pll: Switch to determine_rate | Maxime Ripard | 1 | -7/+12 |
2023-06-09 | ASoC: tlv320aic32x4: Add a determine_rate hook | Maxime Ripard | 1 | -0/+1 |
2020-09-22 | ASoC: tlv320aic32x4: Ensure a minimum delay before clock stabilization | Miquel Raynal | 1 | -1/+8 |
2019-05-02 | ASoC: tlv320aic32x4: Fix potential uninitialized variable | Annaliese McDermond | 1 | -1/+1 |
2019-04-08 | ASoC: tlv320aic32x4: Fix spacing | Annaliese McDermond | 1 | -2/+2 |
2019-03-25 | ASoC: tlv320aic32x4: Model BDIV divider in CCF | Annaliese McDermond | 1 | -0/+36 |
2019-03-25 | ASoC: tlv320aic32x4: Model DAC/ADC dividers in CCF | Annaliese McDermond | 1 | -0/+90 |
2019-03-25 | ASoC: tlv320aic32x4: Model CODEC_CLKIN in CCF | Annaliese McDermond | 1 | -0/+34 |
2019-03-25 | ASoC: tlv320aic32x4: Model PLL in CCF | Annaliese McDermond | 1 | -0/+323 |