summaryrefslogtreecommitdiff
path: root/drivers/clk/renesas/r8a7795-cpg-mssr.c
blob: a85dd50e89110d5d4c571c791a5a8cb87a4d537a (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
/*
 * r8a7795 Clock Pulse Generator / Module Standby and Software Reset
 *
 * Copyright (C) 2015 Glider bvba
 *
 * Based on clk-rcar-gen3.c
 *
 * Copyright (C) 2015 Renesas Electronics Corp.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 */

#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/soc/renesas/rcar-rst.h>
#include <linux/sys_soc.h>

#include <dt-bindings/clock/r8a7795-cpg-mssr.h>

#include "renesas-cpg-mssr.h"
#include "rcar-gen3-cpg.h"

enum clk_ids {
	/* Core Clock Outputs exported to DT */
	LAST_DT_CORE_CLK = R8A7795_CLK_S0D12,

	/* External Input Clocks */
	CLK_EXTAL,
	CLK_EXTALR,

	/* Internal Core Clocks */
	CLK_MAIN,
	CLK_PLL0,
	CLK_PLL1,
	CLK_PLL2,
	CLK_PLL3,
	CLK_PLL4,
	CLK_PLL1_DIV2,
	CLK_PLL1_DIV4,
	CLK_S0,
	CLK_S1,
	CLK_S2,
	CLK_S3,
	CLK_SDSRC,
	CLK_SSPSRC,
	CLK_RINT,

	/* Module Clocks */
	MOD_CLK_BASE
};

static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
	/* External Clock Inputs */
	DEF_INPUT("extal",      CLK_EXTAL),
	DEF_INPUT("extalr",     CLK_EXTALR),

	/* Internal Core Clocks */
	DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
	DEF_BASE(".pll0",       CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
	DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
	DEF_BASE(".pll2",       CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
	DEF_BASE(".pll3",       CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
	DEF_BASE(".pll4",       CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),

	DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,     CLK_PLL1,       2, 1),
	DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4,     CLK_PLL1_DIV2,  2, 1),
	DEF_FIXED(".s0",        CLK_S0,            CLK_PLL1_DIV2,  2, 1),
	DEF_FIXED(".s1",        CLK_S1,            CLK_PLL1_DIV2,  3, 1),
	DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,  4, 1),
	DEF_FIXED(".s3",        CLK_S3,            CLK_PLL1_DIV2,  6, 1),
	DEF_FIXED(".sdsrc",     CLK_SDSRC,         CLK_PLL1_DIV2,  2, 1),

	/* Core Clock Outputs */
	DEF_BASE("z",           R8A7795_CLK_Z,     CLK_TYPE_GEN3_Z, CLK_PLL0),
	DEF_BASE("z2",          R8A7795_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL2),
	DEF_FIXED("ztr",        R8A7795_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
	DEF_FIXED("ztrd2",      R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
	DEF_FIXED("zt",         R8A7795_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
	DEF_FIXED("zx",         R8A7795_CLK_ZX,    CLK_PLL1_DIV2,  2, 1),
	DEF_FIXED("s0d1",       R8A7795_CLK_S0D1,  CLK_S0,         1, 1),
	DEF_FIXED("s0d2",       R8A7795_CLK_S0D2,  CLK_S0,         2, 1),
	DEF_FIXED("s0d3",       R8A7795_CLK_S0D3,  CLK_S0,         3, 1),
	DEF_FIXED("s0d4",       R8A7795_CLK_S0D4,  CLK_S0,         4, 1),
	DEF_FIXED("s0d6",       R8A7795_CLK_S0D6,  CLK_S0,         6, 1),
	DEF_FIXED("s0d8",       R8A7795_CLK_S0D8,  CLK_S0,         8, 1),
	DEF_FIXED("s0d12",      R8A7795_CLK_S0D12, CLK_S0,        12, 1),
	DEF_FIXED("s1d1",       R8A7795_CLK_S1D1,  CLK_S1,         1, 1),
	DEF_FIXED("s1d2",       R8A7795_CLK_S1D2,  CLK_S1,         2, 1),
	DEF_FIXED("s1d4",       R8A7795_CLK_S1D4,  CLK_S1,         4, 1),
	DEF_FIXED("s2d1",       R8A7795_CLK_S2D1,  CLK_S2,         1, 1),
	DEF_FIXED("s2d2",       R8A7795_CLK_S2D2,  CLK_S2,         2, 1),
	DEF_FIXED("s2d4",       R8A7795_CLK_S2D4,  CLK_S2,         4, 1),
	DEF_FIXED("s3d1",       R8A7795_CLK_S3D1,  CLK_S3,         1, 1),
	DEF_FIXED("s3d2",       R8A7795_CLK_S3D2,  CLK_S3,         2, 1),
	DEF_FIXED("s3d4",       R8A7795_CLK_S3D4,  CLK_S3,         4, 1),

	DEF_GEN3_SD("sd0",      R8A7795_CLK_SD0,   CLK_SDSRC,     0x074),
	DEF_GEN3_SD("sd1",      R8A7795_CLK_SD1,   CLK_SDSRC,     0x078),
	DEF_GEN3_SD("sd2",      R8A7795_CLK_SD2,   CLK_SDSRC,     0x268),
	DEF_GEN3_SD("sd3",      R8A7795_CLK_SD3,   CLK_SDSRC,     0x26c),

	DEF_FIXED("cl",         R8A7795_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
	DEF_FIXED("cr",         R8A7795_CLK_CR,    CLK_PLL1_DIV4,  2, 1),
	DEF_FIXED("cp",         R8A7795_CLK_CP,    CLK_EXTAL,      2, 1),

	DEF_DIV6P1("canfd",     R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
	DEF_DIV6P1("csi0",      R8A7795_CLK_CSI0,  CLK_PLL1_DIV4, 0x00c),
	DEF_DIV6P1("mso",       R8A7795_CLK_MSO,   CLK_PLL1_DIV4, 0x014),
	DEF_DIV6P1("hdmi",      R8A7795_CLK_HDMI,  CLK_PLL1_DIV4, 0x250),

	DEF_DIV6_RO("osc",      R8A7795_CLK_OSC,   CLK_EXTAL, CPG_RCKCR,  8),
	DEF_DIV6_RO("r_int",    CLK_RINT,          CLK_EXTAL, CPG_RCKCR, 32),

	DEF_BASE("r",           R8A7795_CLK_R,     CLK_TYPE_GEN3_R, CLK_RINT),
};

static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
	DEF_MOD("fdp1-2",		 117,	R8A7795_CLK_S2D1), /* ES1.x */
	DEF_MOD("fdp1-1",		 118,	R8A7795_CLK_S0D1),
	DEF_MOD("fdp1-0",		 119,	R8A7795_CLK_S0D1),
	DEF_MOD("scif5",		 202,	R8A7795_CLK_S3D4),
	DEF_MOD("scif4",		 203,	R8A7795_CLK_S3D4),
	DEF_MOD("scif3",		 204,	R8A7795_CLK_S3D4),
	DEF_MOD("scif1",		 206,	R8A7795_CLK_S3D4),
	DEF_MOD("scif0",		 207,	R8A7795_CLK_S3D4),
	DEF_MOD("msiof3",		 208,	R8A7795_CLK_MSO),
	DEF_MOD("msiof2",		 209,	R8A7795_CLK_MSO),
	DEF_MOD("msiof1",		 210,	R8A7795_CLK_MSO),
	DEF_MOD("msiof0",		 211,	R8A7795_CLK_MSO),
	DEF_MOD("sys-dmac2",		 217,	R8A7795_CLK_S0D3),
	DEF_MOD("sys-dmac1",		 218,	R8A7795_CLK_S0D3),
	DEF_MOD("sys-dmac0",		 219,	R8A7795_CLK_S0D3),
	DEF_MOD("sceg-pub",		 229,	R8A7795_CLK_CR),
	DEF_MOD("cmt3",			 300,	R8A7795_CLK_R),
	DEF_MOD("cmt2",			 301,	R8A7795_CLK_R),
	DEF_MOD("cmt1",			 302,	R8A7795_CLK_R),
	DEF_MOD("cmt0",			 303,	R8A7795_CLK_R),
	DEF_MOD("scif2",		 310,	R8A7795_CLK_S3D4),
	DEF_MOD("sdif3",		 311,	R8A7795_CLK_SD3),
	DEF_MOD("sdif2",		 312,	R8A7795_CLK_SD2),
	DEF_MOD("sdif1",		 313,	R8A7795_CLK_SD1),
	DEF_MOD("sdif0",		 314,	R8A7795_CLK_SD0),
	DEF_MOD("pcie1",		 318,	R8A7795_CLK_S3D1),
	DEF_MOD("pcie0",		 319,	R8A7795_CLK_S3D1),
	DEF_MOD("usb-dmac30",		 326,	R8A7795_CLK_S3D1),
	DEF_MOD("usb3-if1",		 327,	R8A7795_CLK_S3D1), /* ES1.x */
	DEF_MOD("usb3-if0",		 328,	R8A7795_CLK_S3D1),
	DEF_MOD("usb-dmac31",		 329,	R8A7795_CLK_S3D1),
	DEF_MOD("usb-dmac0",		 330,	R8A7795_CLK_S3D1),
	DEF_MOD("usb-dmac1",		 331,	R8A7795_CLK_S3D1),
	DEF_MOD("rwdt",			 402,	R8A7795_CLK_R),
	DEF_MOD("intc-ex",		 407,	R8A7795_CLK_CP),
	DEF_MOD("intc-ap",		 408,	R8A7795_CLK_S0D3),
	DEF_MOD("audmac1",		 501,	R8A7795_CLK_S0D3),
	DEF_MOD("audmac0",		 502,	R8A7795_CLK_S0D3),
	DEF_MOD("drif7",		 508,	R8A7795_CLK_S3D2),
	DEF_MOD("drif6",		 509,	R8A7795_CLK_S3D2),
	DEF_MOD("drif5",		 510,	R8A7795_CLK_S3D2),
	DEF_MOD("drif4",		 511,	R8A7795_CLK_S3D2),
	DEF_MOD("drif3",		 512,	R8A7795_CLK_S3D2),
	DEF_MOD("drif2",		 513,	R8A7795_CLK_S3D2),
	DEF_MOD("drif1",		 514,	R8A7795_CLK_S3D2),
	DEF_MOD("drif0",		 515,	R8A7795_CLK_S3D2),
	DEF_MOD("hscif4",		 516,	R8A7795_CLK_S3D1),
	DEF_MOD("hscif3",		 517,	R8A7795_CLK_S3D1),
	DEF_MOD("hscif2",		 518,	R8A7795_CLK_S3D1),
	DEF_MOD("hscif1",		 519,	R8A7795_CLK_S3D1),
	DEF_MOD("hscif0",		 520,	R8A7795_CLK_S3D1),
	DEF_MOD("thermal",		 522,	R8A7795_CLK_CP),
	DEF_MOD("pwm",			 523,	R8A7795_CLK_S0D12),
	DEF_MOD("fcpvd3",		 600,	R8A7795_CLK_S2D1), /* ES1.x */
	DEF_MOD("fcpvd2",		 601,	R8A7795_CLK_S0D2),
	DEF_MOD("fcpvd1",		 602,	R8A7795_CLK_S0D2),
	DEF_MOD("fcpvd0",		 603,	R8A7795_CLK_S0D2),
	DEF_MOD("fcpvb1",		 606,	R8A7795_CLK_S0D1),
	DEF_MOD("fcpvb0",		 607,	R8A7795_CLK_S0D1),
	DEF_MOD("fcpvi2",		 609,	R8A7795_CLK_S2D1), /* ES1.x */
	DEF_MOD("fcpvi1",		 610,	R8A7795_CLK_S0D1),
	DEF_MOD("fcpvi0",		 611,	R8A7795_CLK_S0D1),
	DEF_MOD("fcpf2",		 613,	R8A7795_CLK_S2D1), /* ES1.x */
	DEF_MOD("fcpf1",		 614,	R8A7795_CLK_S0D1),
	DEF_MOD("fcpf0",		 615,	R8A7795_CLK_S0D1),
	DEF_MOD("fcpci1",		 616,	R8A7795_CLK_S2D1), /* ES1.x */
	DEF_MOD("fcpci0",		 617,	R8A7795_CLK_S2D1), /* ES1.x */
	DEF_MOD("fcpcs",		 619,	R8A7795_CLK_S0D1),
	DEF_MOD("vspd3",		 620,	R8A7795_CLK_S2D1), /* ES1.x */
	DEF_MOD("vspd2",		 621,	R8A7795_CLK_S0D2),
	DEF_MOD("vspd1",		 622,	R8A7795_CLK_S0D2),
	DEF_MOD("vspd0",		 623,	R8A7795_CLK_S0D2),
	DEF_MOD("vspbc",		 624,	R8A7795_CLK_S0D1),
	DEF_MOD("vspbd",		 626,	R8A7795_CLK_S0D1),
	DEF_MOD("vspi2",		 629,	R8A7795_CLK_S2D1), /* ES1.x */
	DEF_MOD("vspi1",		 630,	R8A7795_CLK_S0D1),
	DEF_MOD("vspi0",		 631,	R8A7795_CLK_S0D1),
	DEF_MOD("ehci3",		 700,	R8A7795_CLK_S3D4),
	DEF_MOD("ehci2",		 701,	R8A7795_CLK_S3D4),
	DEF_MOD("ehci1",		 702,	R8A7795_CLK_S3D4),
	DEF_MOD("ehci0",		 703,	R8A7795_CLK_S3D4),
	DEF_MOD("hsusb",		 704,	R8A7795_CLK_S3D4),
	DEF_MOD("hsusb3",		 705,	R8A7795_CLK_S3D4),
	DEF_MOD("csi21",		 713,	R8A7795_CLK_CSI0), /* ES1.x */
	DEF_MOD("csi20",		 714,	R8A7795_CLK_CSI0),
	DEF_MOD("csi41",		 715,	R8A7795_CLK_CSI0),
	DEF_MOD("csi40",		 716,	R8A7795_CLK_CSI0),
	DEF_MOD("du3",			 721,	R8A7795_CLK_S2D1),
	DEF_MOD("du2",			 722,	R8A7795_CLK_S2D1),
	DEF_MOD("du1",			 723,	R8A7795_CLK_S2D1),
	DEF_MOD("du0",			 724,	R8A7795_CLK_S2D1),
	DEF_MOD("lvds",			 727,	R8A7795_CLK_S0D4),
	DEF_MOD("hdmi1",		 728,	R8A7795_CLK_HDMI),
	DEF_MOD("hdmi0",		 729,	R8A7795_CLK_HDMI),
	DEF_MOD("vin7",			 804,	R8A7795_CLK_S0D2),
	DEF_MOD("vin6",			 805,	R8A7795_CLK_S0D2),
	DEF_MOD("vin5",			 806,	R8A7795_CLK_S0D2),
	DEF_MOD("vin4",			 807,	R8A7795_CLK_S0D2),
	DEF_MOD("vin3",			 808,	R8A7795_CLK_S0D2),
	DEF_MOD("vin2",			 809,	R8A7795_CLK_S0D2),
	DEF_MOD("vin1",			 810,	R8A7795_CLK_S0D2),
	DEF_MOD("vin0",			 811,	R8A7795_CLK_S0D2),
	DEF_MOD("etheravb",		 812,	R8A7795_CLK_S0D6),
	DEF_MOD("sata0",		 815,	R8A7795_CLK_S3D2),
	DEF_MOD("imr3",			 820,	R8A7795_CLK_S0D2),
	DEF_MOD("imr2",			 821,	R8A7795_CLK_S0D2),
	DEF_MOD("imr1",			 822,	R8A7795_CLK_S0D2),
	DEF_MOD("imr0",			 823,	R8A7795_CLK_S0D2),
	DEF_MOD("gpio7",		 905,	R8A7795_CLK_S3D4),
	DEF_MOD("gpio6",		 906,	R8A7795_CLK_S3D4),
	DEF_MOD("gpio5",		 907,	R8A7795_CLK_S3D4),
	DEF_MOD("gpio4",		 908,	R8A7795_CLK_S3D4),
	DEF_MOD("gpio3",		 909,	R8A7795_CLK_S3D4),
	DEF_MOD("gpio2",		 910,	R8A7795_CLK_S3D4),
	DEF_MOD("gpio1",		 911,	R8A7795_CLK_S3D4),
	DEF_MOD("gpio0",		 912,	R8A7795_CLK_S3D4),
	DEF_MOD("can-fd",		 914,	R8A7795_CLK_S3D2),
	DEF_MOD("can-if1",		 915,	R8A7795_CLK_S3D4),
	DEF_MOD("can-if0",		 916,	R8A7795_CLK_S3D4),
	DEF_MOD("i2c6",			 918,	R8A7795_CLK_S0D6),
	DEF_MOD("i2c5",			 919,	R8A7795_CLK_S0D6),
	DEF_MOD("i2c-dvfs",		 926,	R8A7795_CLK_CP),
	DEF_MOD("i2c4",			 927,	R8A7795_CLK_S0D6),
	DEF_MOD("i2c3",			 928,	R8A7795_CLK_S0D6),
	DEF_MOD("i2c2",			 929,	R8A7795_CLK_S3D2),
	DEF_MOD("i2c1",			 930,	R8A7795_CLK_S3D2),
	DEF_MOD("i2c0",			 931,	R8A7795_CLK_S3D2),
	DEF_MOD("ssi-all",		1005,	R8A7795_CLK_S3D4),
	DEF_MOD("ssi9",			1006,	MOD_CLK_ID(1005)),
	DEF_MOD("ssi8",			1007,	MOD_CLK_ID(1005)),
	DEF_MOD("ssi7",			1008,	MOD_CLK_ID(1005)),
	DEF_MOD("ssi6",			1009,	MOD_CLK_ID(1005)),
	DEF_MOD("ssi5",			1010,	MOD_CLK_ID(1005)),
	DEF_MOD("ssi4",			1011,	MOD_CLK_ID(1005)),
	DEF_MOD("ssi3",			1012,	MOD_CLK_ID(1005)),
	DEF_MOD("ssi2",			1013,	MOD_CLK_ID(1005)),
	DEF_MOD("ssi1",			1014,	MOD_CLK_ID(1005)),
	DEF_MOD("ssi0",			1015,	MOD_CLK_ID(1005)),
	DEF_MOD("scu-all",		1017,	R8A7795_CLK_S3D4),
	DEF_MOD("scu-dvc1",		1018,	MOD_CLK_ID(1017)),
	DEF_MOD("scu-dvc0",		1019,	MOD_CLK_ID(1017)),
	DEF_MOD("scu-ctu1-mix1",	1020,	MOD_CLK_ID(1017)),
	DEF_MOD("scu-ctu0-mix0",	1021,	MOD_CLK_ID(1017)),
	DEF_MOD("scu-src9",		1022,	MOD_CLK_ID(1017)),
	DEF_MOD("scu-src8",		1023,	MOD_CLK_ID(1017)),
	DEF_MOD("scu-src7",		1024,	MOD_CLK_ID(1017)),
	DEF_MOD("scu-src6",		1025,	MOD_CLK_ID(1017)),
	DEF_MOD("scu-src5",		1026,	MOD_CLK_ID(1017)),
	DEF_MOD("scu-src4",		1027,	MOD_CLK_ID(1017)),
	DEF_MOD("scu-src3",		1028,	MOD_CLK_ID(1017)),
	DEF_MOD("scu-src2",		1029,	MOD_CLK_ID(1017)),
	DEF_MOD("scu-src1",		1030,	MOD_CLK_ID(1017)),
	DEF_MOD("scu-src0",		1031,	MOD_CLK_ID(1017)),
};

static const unsigned int r8a7795_crit_mod_clks[] __initconst = {
	MOD_CLK_ID(408),	/* INTC-AP (GIC) */
};


/*
 * CPG Clock Data
 */

/*
 *   MD		EXTAL		PLL0	PLL1	PLL2	PLL3	PLL4
 * 14 13 19 17	(MHz)
 *-------------------------------------------------------------------
 * 0  0  0  0	16.66 x 1	x180	x192	x144	x192	x144
 * 0  0  0  1	16.66 x 1	x180	x192	x144	x128	x144
 * 0  0  1  0	Prohibited setting
 * 0  0  1  1	16.66 x 1	x180	x192	x144	x192	x144
 * 0  1  0  0	20    x 1	x150	x160	x120	x160	x120
 * 0  1  0  1	20    x 1	x150	x160	x120	x106	x120
 * 0  1  1  0	Prohibited setting
 * 0  1  1  1	20    x 1	x150	x160	x120	x160	x120
 * 1  0  0  0	25    x 1	x120	x128	x96	x128	x96
 * 1  0  0  1	25    x 1	x120	x128	x96	x84	x96
 * 1  0  1  0	Prohibited setting
 * 1  0  1  1	25    x 1	x120	x128	x96	x128	x96
 * 1  1  0  0	33.33 / 2	x180	x192	x144	x192	x144
 * 1  1  0  1	33.33 / 2	x180	x192	x144	x128	x144
 * 1  1  1  0	Prohibited setting
 * 1  1  1  1	33.33 / 2	x180	x192	x144	x192	x144
 */
#define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 11) | \
					 (((md) & BIT(13)) >> 11) | \
					 (((md) & BIT(19)) >> 18) | \
					 (((md) & BIT(17)) >> 17))

static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
	/* EXTAL div	PLL1 mult/div	PLL3 mult/div */
	{ 1,		192,	1,	192,	1,	},
	{ 1,		192,	1,	128,	1,	},
	{ 0, /* Prohibited setting */			},
	{ 1,		192,	1,	192,	1,	},
	{ 1,		160,	1,	160,	1,	},
	{ 1,		160,	1,	106,	1,	},
	{ 0, /* Prohibited setting */			},
	{ 1,		160,	1,	160,	1,	},
	{ 1,		128,	1,	128,	1,	},
	{ 1,		128,	1,	84,	1,	},
	{ 0, /* Prohibited setting */			},
	{ 1,		128,	1,	128,	1,	},
	{ 2,		192,	1,	192,	1,	},
	{ 2,		192,	1,	128,	1,	},
	{ 0, /* Prohibited setting */			},
	{ 2,		192,	1,	192,	1,	},
};

static const struct soc_device_attribute r8a7795es1[] __initconst = {
	{ .soc_id = "r8a7795", .revision = "ES1.*" },
	{ /* sentinel */ }
};


	/*
	 * Fixups for R-Car H3 ES1.x
	 */

static const unsigned int r8a7795es1_mod_nullify[] __initconst = {
	MOD_CLK_ID(326),			/* USB-DMAC3-0 */
	MOD_CLK_ID(329),			/* USB-DMAC3-1 */
	MOD_CLK_ID(700),			/* EHCI/OHCI3 */
	MOD_CLK_ID(705),			/* HS-USB-IF3 */

};

static const struct mssr_mod_reparent r8a7795es1_mod_reparent[] __initconst = {
	{ MOD_CLK_ID(118), R8A7795_CLK_S2D1 },	/* FDP1-1 */
	{ MOD_CLK_ID(119), R8A7795_CLK_S2D1 },	/* FDP1-0 */
	{ MOD_CLK_ID(217), R8A7795_CLK_S3D1 },	/* SYS-DMAC2 */
	{ MOD_CLK_ID(218), R8A7795_CLK_S3D1 },	/* SYS-DMAC1 */
	{ MOD_CLK_ID(219), R8A7795_CLK_S3D1 },	/* SYS-DMAC0 */
	{ MOD_CLK_ID(408), R8A7795_CLK_S3D1 },	/* INTC-AP */
	{ MOD_CLK_ID(501), R8A7795_CLK_S3D1 },	/* AUDMAC1 */
	{ MOD_CLK_ID(502), R8A7795_CLK_S3D1 },	/* AUDMAC0 */
	{ MOD_CLK_ID(523), R8A7795_CLK_S3D4 },	/* PWM */
	{ MOD_CLK_ID(601), R8A7795_CLK_S2D1 },	/* FCPVD2 */
	{ MOD_CLK_ID(602), R8A7795_CLK_S2D1 },	/* FCPVD1 */
	{ MOD_CLK_ID(603), R8A7795_CLK_S2D1 },	/* FCPVD0 */
	{ MOD_CLK_ID(606), R8A7795_CLK_S2D1 },	/* FCPVB1 */
	{ MOD_CLK_ID(607), R8A7795_CLK_S2D1 },	/* FCPVB0 */
	{ MOD_CLK_ID(610), R8A7795_CLK_S2D1 },	/* FCPVI1 */
	{ MOD_CLK_ID(611), R8A7795_CLK_S2D1 },	/* FCPVI0 */
	{ MOD_CLK_ID(614), R8A7795_CLK_S2D1 },	/* FCPF1 */
	{ MOD_CLK_ID(615), R8A7795_CLK_S2D1 },	/* FCPF0 */
	{ MOD_CLK_ID(619), R8A7795_CLK_S2D1 },	/* FCPCS */
	{ MOD_CLK_ID(621), R8A7795_CLK_S2D1 },	/* VSPD2 */
	{ MOD_CLK_ID(622), R8A7795_CLK_S2D1 },	/* VSPD1 */
	{ MOD_CLK_ID(623), R8A7795_CLK_S2D1 },	/* VSPD0 */
	{ MOD_CLK_ID(624), R8A7795_CLK_S2D1 },	/* VSPBC */
	{ MOD_CLK_ID(626), R8A7795_CLK_S2D1 },	/* VSPBD */
	{ MOD_CLK_ID(630), R8A7795_CLK_S2D1 },	/* VSPI1 */
	{ MOD_CLK_ID(631), R8A7795_CLK_S2D1 },	/* VSPI0 */
	{ MOD_CLK_ID(804), R8A7795_CLK_S2D1 },	/* VIN7 */
	{ MOD_CLK_ID(805), R8A7795_CLK_S2D1 },	/* VIN6 */
	{ MOD_CLK_ID(806), R8A7795_CLK_S2D1 },	/* VIN5 */
	{ MOD_CLK_ID(807), R8A7795_CLK_S2D1 },	/* VIN4 */
	{ MOD_CLK_ID(808), R8A7795_CLK_S2D1 },	/* VIN3 */
	{ MOD_CLK_ID(809), R8A7795_CLK_S2D1 },	/* VIN2 */
	{ MOD_CLK_ID(810), R8A7795_CLK_S2D1 },	/* VIN1 */
	{ MOD_CLK_ID(811), R8A7795_CLK_S2D1 },	/* VIN0 */
	{ MOD_CLK_ID(812), R8A7795_CLK_S3D2 },	/* EAVB-IF */
	{ MOD_CLK_ID(820), R8A7795_CLK_S2D1 },	/* IMR3 */
	{ MOD_CLK_ID(821), R8A7795_CLK_S2D1 },	/* IMR2 */
	{ MOD_CLK_ID(822), R8A7795_CLK_S2D1 },	/* IMR1 */
	{ MOD_CLK_ID(823), R8A7795_CLK_S2D1 },	/* IMR0 */
	{ MOD_CLK_ID(905), R8A7795_CLK_CP },	/* GPIO7 */
	{ MOD_CLK_ID(906), R8A7795_CLK_CP },	/* GPIO6 */
	{ MOD_CLK_ID(907), R8A7795_CLK_CP },	/* GPIO5 */
	{ MOD_CLK_ID(908), R8A7795_CLK_CP },	/* GPIO4 */
	{ MOD_CLK_ID(909), R8A7795_CLK_CP },	/* GPIO3 */
	{ MOD_CLK_ID(910), R8A7795_CLK_CP },	/* GPIO2 */
	{ MOD_CLK_ID(911), R8A7795_CLK_CP },	/* GPIO1 */
	{ MOD_CLK_ID(912), R8A7795_CLK_CP },	/* GPIO0 */
	{ MOD_CLK_ID(918), R8A7795_CLK_S3D2 },	/* I2C6 */
	{ MOD_CLK_ID(919), R8A7795_CLK_S3D2 },	/* I2C5 */
	{ MOD_CLK_ID(927), R8A7795_CLK_S3D2 },	/* I2C4 */
	{ MOD_CLK_ID(928), R8A7795_CLK_S3D2 },	/* I2C3 */
};


	/*
	 * Fixups for R-Car H3 ES2.x
	 */

static const unsigned int r8a7795es2_mod_nullify[] __initconst = {
	MOD_CLK_ID(117),			/* FDP1-2 */
	MOD_CLK_ID(327),			/* USB3-IF1 */
	MOD_CLK_ID(600),			/* FCPVD3 */
	MOD_CLK_ID(609),			/* FCPVI2 */
	MOD_CLK_ID(613),			/* FCPF2 */
	MOD_CLK_ID(616),			/* FCPCI1 */
	MOD_CLK_ID(617),			/* FCPCI0 */
	MOD_CLK_ID(620),			/* VSPD3 */
	MOD_CLK_ID(629),			/* VSPI2 */
	MOD_CLK_ID(713),			/* CSI21 */
};

static int __init r8a7795_cpg_mssr_init(struct device *dev)
{
	const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
	u32 cpg_mode;
	int error;

	error = rcar_rst_read_mode_pins(&cpg_mode);
	if (error)
		return error;

	cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
	if (!cpg_pll_config->extal_div) {
		dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
		return -EINVAL;
	}

	if (soc_device_match(r8a7795es1)) {
		cpg_core_nullify_range(r8a7795_core_clks,
				       ARRAY_SIZE(r8a7795_core_clks),
				       R8A7795_CLK_S0D2, R8A7795_CLK_S0D12);
		mssr_mod_nullify(r8a7795_mod_clks,
				 ARRAY_SIZE(r8a7795_mod_clks),
				 r8a7795es1_mod_nullify,
				 ARRAY_SIZE(r8a7795es1_mod_nullify));
		mssr_mod_reparent(r8a7795_mod_clks,
				  ARRAY_SIZE(r8a7795_mod_clks),
				  r8a7795es1_mod_reparent,
				  ARRAY_SIZE(r8a7795es1_mod_reparent));
	} else {
		mssr_mod_nullify(r8a7795_mod_clks,
				 ARRAY_SIZE(r8a7795_mod_clks),
				 r8a7795es2_mod_nullify,
				 ARRAY_SIZE(r8a7795es2_mod_nullify));
	}

	return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
}

const struct cpg_mssr_info r8a7795_cpg_mssr_info __initconst = {
	/* Core Clocks */
	.core_clks = r8a7795_core_clks,
	.num_core_clks = ARRAY_SIZE(r8a7795_core_clks),
	.last_dt_core_clk = LAST_DT_CORE_CLK,
	.num_total_core_clks = MOD_CLK_BASE,

	/* Module Clocks */
	.mod_clks = r8a7795_mod_clks,
	.num_mod_clks = ARRAY_SIZE(r8a7795_mod_clks),
	.num_hw_mod_clks = 12 * 32,

	/* Critical Module Clocks */
	.crit_mod_clks = r8a7795_crit_mod_clks,
	.num_crit_mod_clks = ARRAY_SIZE(r8a7795_crit_mod_clks),

	/* Callbacks */
	.init = r8a7795_cpg_mssr_init,
	.cpg_clk_register = rcar_gen3_cpg_clk_register,
};