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| author | Rahul Pathak <rpathak@ventanamicro.com> | 2022-08-24 17:54:37 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2022-09-01 13:07:22 +0300 |
| commit | 622cc5f014eb983348aa0dc7fb5fbde43d074782 (patch) | |
| tree | 4cc84a48953e0f6f5e02b2a33e446d9a6287a576 | |
| parent | cbaa9b0333517b3c25bea8d1c71ac8005ff1f727 (diff) | |
| download | opensbi-622cc5f014eb983348aa0dc7fb5fbde43d074782.tar.xz | |
include: Remove sideleg and sedeleg
sideleg and sedeleg csrs are not part of riscv isa spec
anymore, these csrs were part of N extension which
is removed from the riscv isa specification.
These commits removed all traces of these csrs from
riscv spec (https://github.com/riscv/riscv-isa-manual) -
commit f8d27f805b65 ("Remove or downgrade more references to N extension (#674)")
commit b6cade07034d ("Remove N extension chapter for now")
Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
| -rw-r--r-- | include/sbi/riscv_encoding.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h index 8884301..b0f08c8 100644 --- a/include/sbi/riscv_encoding.h +++ b/include/sbi/riscv_encoding.h @@ -312,8 +312,6 @@ /* Supervisor Trap Setup */ #define CSR_SSTATUS 0x100 -#define CSR_SEDELEG 0x102 -#define CSR_SIDELEG 0x103 #define CSR_SIE 0x104 #define CSR_STVEC 0x105 #define CSR_SCOUNTEREN 0x106 |