diff options
| author | Anup Patel <anup.patel@wdc.com> | 2018-12-11 16:54:06 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2018-12-11 16:54:06 +0300 |
| commit | 9e8ff05cb61f157fb0bcb6b0071d7b6dc0763faa (patch) | |
| tree | b9513a86b3b36e569cb46387846fee9c5544f566 /README.md | |
| download | opensbi-9e8ff05cb61f157fb0bcb6b0071d7b6dc0763faa.tar.xz | |
Initial commit.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/README.md b/README.md new file mode 100644 index 0000000..3892273 --- /dev/null +++ b/README.md @@ -0,0 +1,37 @@ +RISC-V Open Source Supervisor Binary Interface (OpenSBI) +======================================================== + +The RISC-V Supervisor Binary Interface (SBI) is a recommended +interface between: +1. platform specific firmware running in M-mode and bootloader + running in S-mode +2. platform specific firmware running in M-mode and general + purpose operating system running in S-mode +3. hypervisor runnng in HS-mode and general purpose operating + system running in VS-mode. + +The RISC-V SBI spec is maintained as independent project by +RISC-V Foundation at https://github.com/riscv/riscv-sbi-doc + +The RISC-V OpenSBI project aims to provides an open-source and +extensible implementation of the SBI spec. This project can be +easily extended by RISC-V platform or RISC-V System-on-Chip vendors. + + +How to Build? +------------- + +Below are the steps to cross-compile and install RISC-V OpenSBI: + +1. Setup build environment +$ CROSS_COMPILE=riscv64-unknown-linux-gnu- + +2. Build sources +$ make PLAT=<platform_name> +OR +$ make PLAT=<platform_name> O=<build_directory> + +3. Install blobs +$ make PLAT=<platform_name> install +OR +$ make PLAT=<platform_name> I=<install_directory> install |