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author | Anup Patel <apatel@ventanamicro.com> | 2022-08-24 12:41:41 +0300 |
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committer | Anup Patel <anup@brainfault.org> | 2022-09-01 14:23:22 +0300 |
commit | d10c1f4acde1753ec5818728e9f864b9838f09d1 (patch) | |
tree | b0b3abcac196e241ff970ac57a7385fa391a20af /include/sbi/sbi_pmu.h | |
parent | c9b388d578647c3283aea03f74bf1251503a58f0 (diff) | |
download | opensbi-d10c1f4acde1753ec5818728e9f864b9838f09d1.tar.xz |
lib: sbi_pmu: Add custom PMU device operations
We extend SBI PMU implementation to allow custom PMU device operations
which a platform can use for platform specific quirks.
The custom PMU device operations added by this patch include:
1) Operations to allow a platform implement custom firmware events.
These custom firmware events can be SBI vendor extension related
events or platform specific per-HART events are not possible to
count through HPM CSRs.
2) Operations to allow a platform implement custom way for enabling
(or disabling) an overflow interrupt (e.g. T-Head C9xx).
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Diffstat (limited to 'include/sbi/sbi_pmu.h')
-rw-r--r-- | include/sbi/sbi_pmu.h | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/include/sbi/sbi_pmu.h b/include/sbi/sbi_pmu.h index 39cf007..d787575 100644 --- a/include/sbi/sbi_pmu.h +++ b/include/sbi/sbi_pmu.h @@ -25,6 +25,63 @@ #define SBI_PMU_CTR_MAX (SBI_PMU_HW_CTR_MAX + SBI_PMU_FW_CTR_MAX) #define SBI_PMU_FIXED_CTR_MASK 0x07 +struct sbi_pmu_device { + /** Name of the PMU platform device */ + char name[32]; + + /** + * Validate event code of custom firmware event + * Note: SBI_PMU_FW_MAX <= event_idx_code + */ + int (*fw_event_validate_code)(uint32_t event_idx_code); + + /** + * Match custom firmware counter with custom firmware event + * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX + */ + bool (*fw_counter_match_code)(uint32_t counter_index, + uint32_t event_idx_code); + + /** + * Read value of custom firmware counter + * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX + */ + uint64_t (*fw_counter_read_value)(uint32_t counter_index); + + /** + * Start custom firmware counter + * Note: SBI_PMU_FW_MAX <= event_idx_code + * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX + */ + int (*fw_counter_start)(uint32_t counter_index, + uint32_t event_idx_code, + uint64_t init_val, bool init_val_update); + + /** + * Stop custom firmware counter + * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX + */ + int (*fw_counter_stop)(uint32_t counter_index); + + /** + * Custom enable irq for hardware counter + * Note: 0 <= counter_index < SBI_PMU_HW_CTR_MAX + */ + void (*hw_counter_enable_irq)(uint32_t counter_index); + + /** + * Custom disable irq for hardware counter + * Note: 0 <= counter_index < SBI_PMU_HW_CTR_MAX + */ + void (*hw_counter_disable_irq)(uint32_t counter_index); +}; + +/** Get the PMU platform device */ +const struct sbi_pmu_device *sbi_pmu_get_device(void); + +/** Set the PMU platform device */ +void sbi_pmu_set_device(const struct sbi_pmu_device *dev); + /** Initialize PMU */ int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot); |