diff options
| author | Yu Chien Peter Lin <peterlin@andestech.com> | 2022-10-14 03:32:43 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2022-10-23 07:53:13 +0300 |
| commit | bd7ef4139829da5c30fa980f7498d385124408fa (patch) | |
| tree | 8007fd4b4d619ee321dc32ac2f026e801f113390 /platform | |
| parent | dcdaf3027489cadd513767eda6dcaa0c1ecd2d29 (diff) | |
| download | opensbi-bd7ef4139829da5c30fa980f7498d385124408fa.tar.xz | |
platform: andes/ae350: Remove enabling cache from an350_final_init
The boot-time cache operations have been handled by U-boot SPL, so we
can drop duplicate code.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'platform')
| -rw-r--r-- | platform/andes/ae350/platform.c | 19 |
1 files changed, 0 insertions, 19 deletions
diff --git a/platform/andes/ae350/platform.c b/platform/andes/ae350/platform.c index 6bd0a69..33f9c4c 100644 --- a/platform/andes/ae350/platform.c +++ b/platform/andes/ae350/platform.c @@ -34,25 +34,6 @@ static int ae350_final_init(bool cold_boot) { void *fdt; - /* enable L1 cache */ - uintptr_t mcache_ctl_val = csr_read(CSR_MCACHECTL); - - if (!(mcache_ctl_val & V5_MCACHE_CTL_IC_EN)) - mcache_ctl_val |= V5_MCACHE_CTL_IC_EN; - if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_EN)) - mcache_ctl_val |= V5_MCACHE_CTL_DC_EN; - if (!(mcache_ctl_val & V5_MCACHE_CTL_CCTL_SUEN)) - mcache_ctl_val |= V5_MCACHE_CTL_CCTL_SUEN; - csr_write(CSR_MCACHECTL, mcache_ctl_val); - - /* enable L2 cache */ - uint32_t *l2c_ctl_base = (void *)AE350_L2C_ADDR + V5_L2C_CTL_OFFSET; - uint32_t l2c_ctl_val = *l2c_ctl_base; - - if (!(l2c_ctl_val & V5_L2C_CTL_ENABLE_MASK)) - l2c_ctl_val |= V5_L2C_CTL_ENABLE_MASK; - *l2c_ctl_base = l2c_ctl_val; - if (!cold_boot) return 0; |