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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2018-09-10 05:17:30 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-09-10 21:08:22 +0300 |
| commit | e8f65763ef07e0667f57dda7eece657f8fe136a7 (patch) | |
| tree | 5617885c06640864e07d33b2f1236bef576f2eda /.travis.yml | |
| parent | f850371997fb3688885a814902fed07d22f113ef (diff) | |
| download | u-boot-e8f65763ef07e0667f57dda7eece657f8fe136a7.tar.xz | |
mtd: nand: denali: fix unaligned cache operations on ARMv7 SoCs
If the OOB size is not multiple of the cache line size, the ARMv7
cache operation still prints "Misaligned operation at range".
=> nand info
Device 0: nand0, sector size 256 KiB
Page size 4096 b
OOB size 224 b
Erase size 262144 b
subpagesize 4096 b
options 0x00104200
bbt options 0x00060000
=> nand dump 0
CACHE: Misaligned operation at range [9fb15280, 9fb16360]
CACHE: Misaligned operation at range [9fb15280, 9fb16360]
CACHE: Misaligned operation at range [9fb15280, 9fb16360]
CACHE: Misaligned operation at range [9fb15280, 9fb16360]
...
The cache flushing operations won't happen in this case to cover all of
the range to fix this by making sure we have things aligned.
Reported-by: Marek Vasut <marex@denx.de>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Reword the commit message to be clear this is a direct problem
rather than just a warning]
Diffstat (limited to '.travis.yml')
0 files changed, 0 insertions, 0 deletions