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| author | Wei Liang Lim <weiliang.lim@starfivetech.com> | 2023-10-19 13:09:08 +0300 |
|---|---|---|
| committer | Wei Liang Lim <weiliang.lim@starfivetech.com> | 2023-10-19 13:09:08 +0300 |
| commit | 7bf446101651767e3a2de7227889004166ec34d6 (patch) | |
| tree | 7575a03d7aa83c1c9fdafcd5f5d1b573457cea73 | |
| parent | aad6f73d21a428f87d2c6fb8a0dabd96b5287e96 (diff) | |
| download | u-boot-7bf446101651767e3a2de7227889004166ec34d6.tar.xz | |
riscv: dubhe: Set SYS_CACHELINE_SIZE 64
Signed-off-by: Wei Liang Lim <weiliang.lim@starfivetech.com>
| -rw-r--r-- | arch/riscv/cpu/dubhe/Kconfig | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/riscv/cpu/dubhe/Kconfig b/arch/riscv/cpu/dubhe/Kconfig index 38e94c96a4..7f0ce08a39 100644 --- a/arch/riscv/cpu/dubhe/Kconfig +++ b/arch/riscv/cpu/dubhe/Kconfig @@ -16,3 +16,6 @@ config STARFIVE_DUBHE imply SPL_OPENSBI imply SPL_LOAD_FIT imply MII + +config SYS_CACHELINE_SIZE + default 64 |