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| author | Xingyu Wu <xingyu.wu@starfivetech.com> | 2023-07-07 13:50:08 +0300 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-07-24 08:21:01 +0300 |
| commit | 005f9627d02e8ecab3c58c77889060e72f7fa25d (patch) | |
| tree | b63fe4485552248aba0081de015f913ddd4c1243 | |
| parent | 2d7a5787915716040ec381d1cf5064a3401ed12a (diff) | |
| download | u-boot-005f9627d02e8ecab3c58c77889060e72f7fa25d.tar.xz | |
riscv: dts: jh7110: Add PLL clock controller node
Add child node about PLL clock controller in sys_syscon node.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
| -rw-r--r-- | arch/riscv/dts/jh7110.dtsi | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index 58e332e9d7..7a8141a8e9 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b/arch/riscv/dts/jh7110.dtsi @@ -498,8 +498,14 @@ }; sys_syscon: sys_syscon@13030000 { - compatible = "starfive,jh7110-sys-syscon","syscon"; + compatible = "starfive,jh7110-sys-syscon","syscon", "simple-mfd"; reg = <0x0 0x13030000 0x0 0x1000>; + + pllclk: clock-controller { + compatible = "starfive,jh7110-pll"; + clocks = <&osc>; + #clock-cells = <1>; + }; }; sysgpio: pinctrl@13040000 { |