diff options
| author | Yangbo Lu <yangbo.lu@nxp.com> | 2019-10-31 13:54:25 +0300 |
|---|---|---|
| committer | Peng Fan <peng.fan@nxp.com> | 2019-11-05 06:21:25 +0300 |
| commit | 0cc127c424ea313b1afc3e53f7c1ba248961728e (patch) | |
| tree | 4d92c1a8e0c2860b133557033e9ced3987f6f841 | |
| parent | 08197cb8dff7cd097ab07a325093043c39d19bbd (diff) | |
| download | u-boot-0cc127c424ea313b1afc3e53f7c1ba248961728e.tar.xz | |
mmc: fsl_esdhc: always check write protect state
The QorIQ eSDHC on all platforms supports checking write protect
state through register bit. So check it always.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
| -rw-r--r-- | drivers/mmc/fsl_esdhc.c | 15 | ||||
| -rw-r--r-- | include/fsl_esdhc.h | 1 |
2 files changed, 4 insertions, 12 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 25a8fe3480..bdc0ca6197 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -75,7 +75,6 @@ struct fsl_esdhc_plat { * @mmc: mmc * Following is used when Driver Model is enabled for MMC * @dev: pointer for the device - * @wp_enable: 1: enable checking wp; 0: no check * @cd_gpio: gpio for card detection * @wp_gpio: gpio for write protection */ @@ -88,7 +87,6 @@ struct fsl_esdhc_priv { struct mmc *mmc; #endif struct udevice *dev; - int wp_enable; }; /* Return the XFERTYP flags for a given command and data packet */ @@ -231,12 +229,10 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, #endif if (wml_value > WML_WR_WML_MAX) wml_value = WML_WR_WML_MAX_VAL; - if (priv->wp_enable) { - if ((esdhc_read32(®s->prsstat) & - PRSSTAT_WPSPL) == 0) { - printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); - return -ETIMEDOUT; - } + + if (!(esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL)) { + printf("Can not write to locked SD card.\n"); + return -EINVAL; } esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, @@ -722,7 +718,6 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base); priv->sdhc_clk = cfg->sdhc_clk; - priv->wp_enable = cfg->wp_enable; mmc_cfg = &plat->cfg; @@ -862,8 +857,6 @@ static int fsl_esdhc_probe(struct udevice *dev) #endif priv->dev = dev; - priv->wp_enable = 1; - if (IS_ENABLED(CONFIG_CLK)) { /* Assigned clock already set clock */ ret = clk_get_by_name(dev, "per", &priv->per_clk); diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index a015df1cec..8e8cd2cc1a 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -168,7 +168,6 @@ struct fsl_esdhc_cfg { phys_addr_t esdhc_base; u32 sdhc_clk; u8 max_bus_width; - int wp_enable; int vs18_enable; /* Use 1.8V if set to 1 */ struct mmc_config cfg; }; |