diff options
| author | Hal Feng <hal.feng@starfivetech.com> | 2023-08-09 11:02:50 +0300 |
|---|---|---|
| committer | Hal Feng <hal.feng@starfivetech.com> | 2023-11-29 05:53:10 +0300 |
| commit | 55255733cfcd7735b9390c324d5f451f4ebbac23 (patch) | |
| tree | 005be2eb3496f246e5389600fe1fdafae56f55bf | |
| parent | e4f8517ebf5ae7a80540f11dde02868c85d21a24 (diff) | |
| download | u-boot-55255733cfcd7735b9390c324d5f451f4ebbac23.tar.xz | |
riscv: dts: jh7110: Sync with Devkits repo
To be compatible with the Devkits board.
The code is ported from tag JH7110_DVK_515_v3.9.3 of Devkits repo.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
| -rw-r--r-- | arch/riscv/dts/jh7110-u-boot.dtsi | 8 | ||||
| -rw-r--r-- | arch/riscv/dts/jh7110.dtsi | 52 |
2 files changed, 47 insertions, 13 deletions
diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi index e45b6cde3b..37586fdc15 100644 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -129,3 +129,11 @@ &gmac0_rmii_refin { u-boot,dm-spl; }; + +&gpio { + u-boot,dm-spl; +}; + +&gpioa { + u-boot,dm-spl; +}; diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index de5289cff5..d8f62454fd 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b/arch/riscv/dts/jh7110.dtsi @@ -623,19 +623,6 @@ status = "disabled"; }; - i2c6: i2c@12060000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0x12060000 0x0 0x10000>; - clocks = <&clkgen JH7110_I2C6_CLK_CORE>, - <&clkgen JH7110_I2C6_CLK_APB>; - clock-names = "ref", "pclk"; - resets = <&rstgen RSTN_U6_DW_I2C_APB>; - interrupts = <51>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - i2c0: i2c@10030000 { compatible = "snps,designware-i2c"; reg = <0x0 0x10030000 0x0 0x10000>; @@ -675,6 +662,32 @@ status = "disabled"; }; + i2c3: i2c@12030000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x12030000 0x0 0x10000>; + clocks = <&clkgen JH7110_I2C3_CLK_CORE>, + <&clkgen JH7110_I2C3_CLK_APB>; + clock-names = "ref", "pclk"; + resets = <&rstgen RSTN_U3_DW_I2C_APB>; + interrupts = <48>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@12040000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x12040000 0x0 0x10000>; + clocks = <&clkgen JH7110_I2C4_CLK_CORE>, + <&clkgen JH7110_I2C4_CLK_APB>; + clock-names = "ref", "pclk"; + resets = <&rstgen RSTN_U4_DW_I2C_APB>; + interrupts = <49>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c5: i2c@12050000 { compatible = "snps,designware-i2c"; reg = <0x0 0x12050000 0x0 0x10000>; @@ -688,6 +701,19 @@ status = "disabled"; }; + i2c6: i2c@12060000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x12060000 0x0 0x10000>; + clocks = <&clkgen JH7110_I2C6_CLK_CORE>, + <&clkgen JH7110_I2C6_CLK_APB>; + clock-names = "ref", "pclk"; + resets = <&rstgen RSTN_U6_DW_I2C_APB>; + interrupts = <51>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + /* unremovable emmc as mmcblk0 */ sdio0: sdio0@16010000 { compatible = "snps,dw-mshc"; |