m68k: Remove M54451EVB board

This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.  As this is also the last in family remove the related
support as well.

Cc: Angelo Durgehello <angelo.dureghello@timesys.com>
Signed-off-by: Tom Rini <trini@konsulko.com>

23 files changed, 1 insertions, 2254 deletions

diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index c48b8a543d..2d47141841 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -53,12 +53,6 @@ config MCF5441x
         select DM_SERIAL
 	bool
 
-config MCF5445x
-	select OF_CONTROL
-	select DM
-        select DM_SERIAL
-	bool
-
 config MCF5227x
 	select OF_CONTROL
 	select DM
@@ -119,10 +113,6 @@ config M54418
 	bool
 	select MCF5441x
 
-config M54451
-	bool
-	select MCF5445x
-
 config M52277
 	bool
 	select MCF5227x
@@ -187,10 +177,6 @@ config TARGET_M5373EVB
 	bool "Support M5373EVB"
 	select M5373
 
-config TARGET_M54451EVB
-	bool "Support M54451EVB"
-	select M54451
-
 config TARGET_AMCORE
 	bool "Support AMCORE"
 	select M5307
@@ -215,7 +201,6 @@ source "board/freescale/m5282evb/Kconfig"
 source "board/freescale/m53017evb/Kconfig"
 source "board/freescale/m5329evb/Kconfig"
 source "board/freescale/m5373evb/Kconfig"
-source "board/freescale/m54451evb/Kconfig"
 source "board/sysam/amcore/Kconfig"
 source "board/sysam/stmark2/Kconfig"
 
diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile
index 86b36e1a40..63f18109a5 100644
--- a/arch/m68k/Makefile
+++ b/arch/m68k/Makefile
@@ -18,13 +18,11 @@ cpuflags-$(CONFIG_M5307)	:= -mcpu=5307
 cpuflags-$(CONFIG_MCF5301x)	:= -mcpu=53015 -fPIC
 cpuflags-$(CONFIG_MCF532x)	:= -mcpu=5329 -fPIC
 cpuflags-$(CONFIG_MCF5441x)	:= -mcpu=54418 -fPIC
-cpuflags-$(CONFIG_MCF5445x)	:= -mcpu=54455 -fPIC
 
 PLATFORM_CPPFLAGS += $(cpuflags-y)
 
 
 ldflags-$(CONFIG_MCF5441x)	:= --got=single
-ldflags-$(CONFIG_MCF5445x)	:= --got=single
 
 ifneq (,$(findstring -linux-,$(shell $(CC) --version)))
 ifneq (,$(findstring GOT,$(shell $(LD) --help)))
diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c
index 9deab51d07..9b3f9f0fe1 100644
--- a/arch/m68k/cpu/mcf5445x/cpu_init.c
+++ b/arch/m68k/cpu/mcf5445x/cpu_init.c
@@ -73,13 +73,6 @@ void cfspi_port_conf(void)
 {
 	gpio_t *gpio = (gpio_t *)MMAP_GPIO;
 
-#ifdef CONFIG_MCF5445x
-	out_8(&gpio->par_dspi,
-	      GPIO_PAR_DSPI_SIN_SIN |
-	      GPIO_PAR_DSPI_SOUT_SOUT |
-	      GPIO_PAR_DSPI_SCK_SCK);
-#endif
-
 #ifdef CONFIG_MCF5441x
 	pm_t *pm = (pm_t *)MMAP_PM;
 
@@ -212,36 +205,6 @@ void cpu_init_f(void)
 #endif
 #endif		/* CONFIG_MCF5441x */
 
-#ifdef CONFIG_MCF5445x
-	scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
-
-	out_be32(&scm1->mpr, 0x77777777);
-	out_be32(&scm1->pacra, 0);
-	out_be32(&scm1->pacrb, 0);
-	out_be32(&scm1->pacrc, 0);
-	out_be32(&scm1->pacrd, 0);
-	out_be32(&scm1->pacre, 0);
-	out_be32(&scm1->pacrf, 0);
-	out_be32(&scm1->pacrg, 0);
-
-	/* FlexBus */
-	out_8(&gpio->par_be,
-		GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
-		GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
-	out_8(&gpio->par_fbctl,
-		GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
-		GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
-
-#ifdef CONFIG_CF_SPI
-	cfspi_port_conf();
-#endif
-
-#ifdef CONFIG_SYS_FSL_I2C
-	out_be16(&gpio->par_feci2c,
-		GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
-#endif
-#endif		/* CONFIG_MCF5445x */
-
 	/* FlexBus Chipselect */
 	init_fbcs();
 
@@ -365,40 +328,6 @@ void uart_port_conf(int port)
 			GPIO_PAR_CANI2C_CAN1TX_U9TXD | GPIO_PAR_CANI2C_CAN1RX_U9RXD);
 		break;
 #endif
-#ifdef CONFIG_MCF5445x
-	case 0:
-		clrbits_8(&gpio->par_uart,
-			GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
-		setbits_8(&gpio->par_uart,
-			GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
-		break;
-	case 1:
-#ifdef CONFIG_SYS_UART1_PRI_GPIO
-		clrbits_8(&gpio->par_uart,
-			GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
-		setbits_8(&gpio->par_uart,
-			GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
-#elif defined(CONFIG_SYS_UART1_ALT1_GPIO)
-		clrbits_be16(&gpio->par_ssi,
-			~(GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK));
-		setbits_be16(&gpio->par_ssi,
-			GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD);
-#endif
-		break;
-	case 2:
-#if defined(CONFIG_SYS_UART2_ALT1_GPIO)
-		clrbits_8(&gpio->par_timer,
-			~(GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK));
-		setbits_8(&gpio->par_timer,
-			GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD);
-#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
-		clrbits_8(&gpio->par_timer,
-			~(GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK));
-		setbits_8(&gpio->par_timer,
-			GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD);
-#endif
-		break;
-#endif	/* CONFIG_MCF5445x */
 	}
 }
 
@@ -411,46 +340,6 @@ int fecpin_setclear(fec_info_t *info, int setclear)
 	if (fec_get_base_addr(0, &fec0_base))
 		return -1;
 
-#ifdef CONFIG_MCF5445x
-	if (setclear) {
-#ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
-		if (info->iobase == fec0_base)
-			setbits_be16(&gpio->par_feci2c,
-				GPIO_PAR_FECI2C_MDC0_MDC0 |
-				GPIO_PAR_FECI2C_MDIO0_MDIO0);
-		else
-			setbits_be16(&gpio->par_feci2c,
-				GPIO_PAR_FECI2C_MDC1_MDC1 |
-				GPIO_PAR_FECI2C_MDIO1_MDIO1);
-#else
-		setbits_be16(&gpio->par_feci2c,
-			GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
-#endif
-
-		if (info->iobase == fec0_base)
-			setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_RMII_GPIO);
-		else
-			setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_RMII_ATA);
-	} else {
-		clrbits_be16(&gpio->par_feci2c,
-			GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
-
-		if (info->iobase == fec0_base) {
-#ifdef CONFIG_SYS_FEC_FULL_MII
-			setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_MII);
-#else
-			clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC0_UNMASK);
-#endif
-		} else {
-#ifdef CONFIG_SYS_FEC_FULL_MII
-			setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_MII);
-#else
-			clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC1_UNMASK);
-#endif
-		}
-	}
-#endif	/* CONFIG_MCF5445x */
-
 #ifdef CONFIG_MCF5441x
 	if (setclear) {
 		out_8(&gpio->par_fec, 0x03);
diff --git a/arch/m68k/cpu/mcf5445x/dspi.c b/arch/m68k/cpu/mcf5445x/dspi.c
index b0e2f2cb01..456af171a4 100644
--- a/arch/m68k/cpu/mcf5445x/dspi.c
+++ b/arch/m68k/cpu/mcf5445x/dspi.c
@@ -15,30 +15,6 @@ void dspi_chip_select(int cs)
 {
 	struct gpio *gpio = (struct gpio *)MMAP_GPIO;
 
-#ifdef CONFIG_MCF5445x
-	switch (cs) {
-	case 0:
-		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
-		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
-		break;
-	case 1:
-		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
-		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
-		break;
-	case 2:
-		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
-		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
-		break;
-	case 3:
-		clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
-		setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3);
-		break;
-	case 5:
-		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
-		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
-		break;
-	}
-#endif
 #ifdef CONFIG_MCF5441x
 	switch (cs) {
 	case 0:
@@ -61,25 +37,6 @@ void dspi_chip_unselect(int cs)
 {
 	struct gpio *gpio = (struct gpio *)MMAP_GPIO;
 
-#ifdef CONFIG_MCF5445x
-	switch (cs) {
-	case 0:
-		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
-		break;
-	case 1:
-		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
-		break;
-	case 2:
-		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
-		break;
-	case 3:
-		clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
-		break;
-	case 5:
-		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
-		break;
-	}
-#endif
 #ifdef CONFIG_MCF5441x
 	if (cs == 1)
 		clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
diff --git a/arch/m68k/cpu/mcf5445x/speed.c b/arch/m68k/cpu/mcf5445x/speed.c
index 4809bb49d1..eb73da68c6 100644
--- a/arch/m68k/cpu/mcf5445x/speed.c
+++ b/arch/m68k/cpu/mcf5445x/speed.c
@@ -42,11 +42,6 @@ void clock_enter_limp(int lpdiv)
 	/* Round divider down to nearest power of two */
 	for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
 
-#ifdef CONFIG_MCF5445x
-	/* Apply the divider to the system clock */
-	clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
-#endif
-
 	/* Enable Limp Mode */
 	setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
 }
@@ -127,135 +122,12 @@ void setup_5441x_clocks(void)
 }
 #endif
 
-#ifdef CONFIG_MCF5445x
-void setup_5445x_clocks(void)
-{
-	ccm_t *ccm = (ccm_t *)MMAP_CCM;
-	pll_t *pll = (pll_t *)MMAP_PLL;
-	int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
-	int pllmult_pci[] = { 12, 6, 16, 8 };
-	int vco = 0, temp, fbtemp, pcrvalue;
-	int *pPllmult = NULL;
-	u16 fbpll_mask;
-#ifdef CONFIG_PCI
-	int bPci;
-#endif
-
-	u8 bootmode;
-
-	/* To determine PCI is present or not */
-	if (((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) ||
-	    ((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
-		pPllmult = &pllmult_pci[0];
-		fbpll_mask = 3;		/* 11b */
-#ifdef CONFIG_PCI
-		bPci = 1;
-#endif
-	} else {
-		pPllmult = &pllmult_nopci[0];
-		fbpll_mask = 7;		/* 111b */
-#ifdef CONFIG_PCI
-		gd->pci_clk = 0;
-		bPci = 0;
-#endif
-	}
-
-#ifdef CONFIG_M54451EVB
-	/* No external logic to read the bootmode, hard coded from built */
-#ifdef CONFIG_CF_SBF
-	bootmode = 3;
-#else
-	bootmode = 2;
-
-	/* default value is 16 mul, set to 20 mul */
-	pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF) | 0x14000000;
-	out_be32(&pll->pcr, pcrvalue);
-	while ((in_be32(&pll->psr) & PLL_PSR_LOCK) != PLL_PSR_LOCK)
-		;
-#endif
-#endif
-
-	if (bootmode == 0) {
-		/* RCON mode */
-		vco = pPllmult[ccm->rcon & fbpll_mask] * CONFIG_SYS_INPUT_CLKSRC;
-
-		if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
-			/* invaild range, re-set in PCR */
-			int temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
-			int i, j, bus;
-
-			j = (in_be32(&pll->pcr) & 0xFF000000) >> 24;
-			for (i = j; i < 0xFF; i++) {
-				vco = i * CONFIG_SYS_INPUT_CLKSRC;
-				if (vco >= CLOCK_PLL_FVCO_MIN) {
-					bus = vco / temp;
-					if (bus <= CLOCK_PLL_FSYS_MIN - MHZ)
-						continue;
-					else
-						break;
-				}
-			}
-			pcrvalue = in_be32(&pll->pcr) & 0x00FF00FF;
-			fbtemp = ((i - 1) << 8) | ((i - 1) << 12);
-			pcrvalue |= ((i << 24) | fbtemp);
-
-			out_be32(&pll->pcr, pcrvalue);
-		}
-		gd->arch.vco_clk = vco;	/* Vco clock */
-	} else if (bootmode == 2) {
-		/* Normal mode */
-		vco =  ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
-		if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
-			/* Default value */
-			pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
-			pcrvalue |= pPllmult[in_be16(&ccm->ccr) & fbpll_mask] << 24;
-			out_be32(&pll->pcr, pcrvalue);
-			vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
-		}
-		gd->arch.vco_clk = vco;	/* Vco clock */
-	} else if (bootmode == 3) {
-		/* serial mode */
-		vco =  ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
-		gd->arch.vco_clk = vco;	/* Vco clock */
-	}
-
-	if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
-		/* Limp mode */
-	} else {
-		gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
-
-		temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
-		gd->cpu_clk = vco / temp;	/* cpu clock */
-
-		temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
-		gd->bus_clk = vco / temp;	/* bus clock */
-
-		temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV3_MASK) >> 8) + 1;
-		gd->arch.flb_clk = vco / temp;	/* FlexBus clock */
-
-#ifdef CONFIG_PCI
-		if (bPci) {
-			temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV4_MASK) >> 12) + 1;
-			gd->pci_clk = vco / temp;	/* PCI clock */
-		}
-#endif
-	}
-
-#ifdef CONFIG_SYS_I2C_FSL
-	gd->arch.i2c1_clk = gd->bus_clk;
-#endif
-}
-#endif
-
 /* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
 int get_clocks(void)
 {
 #ifdef CONFIG_MCF5441x
 	setup_5441x_clocks();
 #endif
-#ifdef CONFIG_MCF5445x
-	setup_5445x_clocks();
-#endif
 
 #ifdef CONFIG_SYS_FSL_I2C
 	gd->arch.i2c1_clk = gd->bus_clk;
diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S
index 80eb287151..7007d78c83 100644
--- a/arch/m68k/cpu/mcf5445x/start.S
+++ b/arch/m68k/cpu/mcf5445x/start.S
@@ -202,10 +202,6 @@ asm_dspi_init:
 	move.b	#0x80, (%a2)
 #endif
 
-#ifdef CONFIG_MCF5445x
-	move.l	#0xFC0A4063, %a0
-	move.b	#0x7F, (%a0)
-#endif
 	/* Configure DSPI module */
 	move.l	#0xFC05C000, %a0
 	move.l	#0x80FF0C00, (%a0)	/* Master, clear TX/RX FIFO */
@@ -214,9 +210,6 @@ asm_dspi_init:
 #ifdef CONFIG_MCF5441x
 	move.l	#0x3E000016, (%a0)
 #endif
-#ifdef CONFIG_MCF5445x
-	move.l	#0x3E000011, (%a0)
-#endif
 
 	move.l	#0xFC05C034, %a2	/* dtfr */
 	move.l	#0xFC05C03B, %a3	/* drfr */
diff --git a/arch/m68k/dts/M54451EVB.dts b/arch/m68k/dts/M54451EVB.dts
deleted file mode 100644
index b81d37a938..0000000000
--- a/arch/m68k/dts/M54451EVB.dts
+++ /dev/null
@@ -1,33 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf5445x.dtsi"
-
-/ {
-	model = "Freescale M54451EVB";
-	compatible = "fsl,M54451EVB";
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-};
-
-&uart0 {
-	u-boot,dm-pre-reloc;
-	status = "okay";
-};
-
-&dspi0 {
-	status = "okay";
-};
-
-&fec0 {
-	status = "okay";
-};
-
-&fec1 {
-	status = "okay";
-};
diff --git a/arch/m68k/dts/M54451EVB_stmicro.dts b/arch/m68k/dts/M54451EVB_stmicro.dts
deleted file mode 100644
index 6645b58065..0000000000
--- a/arch/m68k/dts/M54451EVB_stmicro.dts
+++ /dev/null
@@ -1,33 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf5445x.dtsi"
-
-/ {
-	model = "Freescale M54451EVB_stmicro";
-	compatible = "fsl,M54451EVB";
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-};
-
-&uart0 {
-	u-boot,dm-pre-reloc;
-	status = "okay";
-};
-
-&dspi0 {
-	status = "okay";
-};
-
-&fec0 {
-	status = "okay";
-};
-
-&fec1 {
-	status = "okay";
-};
diff --git a/arch/m68k/dts/Makefile b/arch/m68k/dts/Makefile
index 829edb8dbc..49618e64fe 100644
--- a/arch/m68k/dts/Makefile
+++ b/arch/m68k/dts/Makefile
@@ -17,8 +17,6 @@ dtb-$(CONFIG_TARGET_ASTRO_MCF5373L) += astro_mcf5373l.dtb
 dtb-$(CONFIG_TARGET_M53017EVB) += M53017EVB.dtb
 dtb-$(CONFIG_TARGET_M5329EVB) += M5329AFEE.dtb M5329BFEE.dtb
 dtb-$(CONFIG_TARGET_M5373EVB) += M5373EVB.dtb
-dtb-$(CONFIG_TARGET_M54451EVB) += M54451EVB.dtb \
-	M54451EVB_stmicro.dtb
 dtb-$(CONFIG_TARGET_AMCORE) += amcore.dtb
 dtb-$(CONFIG_TARGET_STMARK2) += stmark2.dtb
 
diff --git a/arch/m68k/dts/mcf5445x.dtsi b/arch/m68k/dts/mcf5445x.dtsi
deleted file mode 100644
index b7ecc99c09..0000000000
--- a/arch/m68k/dts/mcf5445x.dtsi
+++ /dev/null
@@ -1,68 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/ {
-	compatible = "fsl,mcf5445x";
-
-	aliases {
-		serial0 = &uart0;
-		spi0 = &dspi0;
-		fec0 = &fec0;
-		fec1 = &fec1;
-	};
-
-	soc {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		uart0: uart@fc060000 {
-			compatible = "fsl,mcf-uart";
-			reg = <0xfc060000 0x40>;
-			status = "disabled";
-		};
-
-		uart1: uart@fc064000 {
-			compatible = "fsl,mcf-uart";
-			reg = <0xfc064000 0x40>;
-			status = "disabled";
-		};
-
-		uart2: uart@fc068000 {
-			compatible = "fsl,mcf-uart";
-			reg = <0xfc068000 0x40>;
-			status = "disabled";
-		};
-
-		dspi0: dspi@fc05c000 {
-			compatible = "fsl,mcf-dspi";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0xfc05c000 0x100>;
-			spi-max-frequency = <50000000>;
-			num-cs = <4>;
-			spi-mode = <0>;
-			status = "disabled";
-		};
-
-		fec0: ethernet@fc030000 {
-			compatible = "fsl,mcf-fec";
-			reg = <0xfc030000 0x4000>;
-			mii-base = <0>;
-			max-speed = <100>;
-			timeout-loop = <50000>;
-			status = "disabled";
-		};
-
-		fec1: ethernet@fc034000 {
-			compatible = "fsl,mcf-fec";
-			reg = <0xfc034000 0x4000>;
-			mii-base = <1>;
-			max-speed = <100>;
-			timeout-loop = <50000>;
-			status = "disabled";
-		};
-	};
-};
diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h
index fabec0ae92..1c04d6df7c 100644
--- a/arch/m68k/include/asm/cache.h
+++ b/arch/m68k/include/asm/cache.h
@@ -19,9 +19,7 @@
 #define CONFIG_CF_V3
 #endif
 
-#if defined(CONFIG_MCF5445x)
-#define CONFIG_CF_V4
-#elif defined(CONFIG_MCF5441x)
+#if defined(CONFIG_MCF5441x)
 #define CONFIG_CF_V4E		/* Four Extra ACRn */
 #endif
 
diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h
index 07d9745b14..81837a7c16 100644
--- a/arch/m68k/include/asm/immap.h
+++ b/arch/m68k/include/asm/immap.h
@@ -330,39 +330,6 @@
 
 #endif				/* CONFIG_M54418 */
 
-#if defined(CONFIG_M54451)
-#include <asm/immap_5445x.h>
-#include <asm/m5445x.h>
-
-#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
-
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
-
-#define CONFIG_SYS_MCFRTC_BASE		(MMAP_RTC)
-
-/* Timer */
-#ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
-#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
-#define CONFIG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
-#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRH_INT33)
-#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI		(6)
-#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
-#endif
-
-#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS		(128)
-
-#ifdef CONFIG_PCI
-#define CONFIG_SYS_PCI_BAR0		(CONFIG_SYS_MBAR)
-#define CONFIG_SYS_PCI_BAR5		(CONFIG_SYS_SDRAM_BASE)
-#define CONFIG_SYS_PCI_TBATR0		(CONFIG_SYS_MBAR)
-#define CONFIG_SYS_PCI_TBATR5		(CONFIG_SYS_SDRAM_BASE)
-#endif
-#endif				/* CONFIG_M54451 */
-
 #ifdef CONFIG_M547x
 #include <asm/immap_547x_8x.h>
 #include <asm/m547x_8x.h>
diff --git a/arch/m68k/include/asm/immap_5445x.h b/arch/m68k/include/asm/immap_5445x.h
deleted file mode 100644
index 3111d00d3e..0000000000
--- a/arch/m68k/include/asm/immap_5445x.h
+++ /dev/null
@@ -1,335 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * MCF5445x Internal Memory Map
- *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-#ifndef __IMMAP_5445X__
-#define __IMMAP_5445X__
-
-/* Module Base Addresses */
-#define MMAP_SCM1	0xFC000000
-#define MMAP_XBS	0xFC004000
-#define MMAP_FBCS	0xFC008000
-#define MMAP_FEC0	0xFC030000
-#define MMAP_FEC1	0xFC034000
-#define MMAP_RTC	0xFC03C000
-#define MMAP_SCM2	0xFC040000
-#define MMAP_EDMA	0xFC044000
-#define MMAP_INTC0	0xFC048000
-#define MMAP_INTC1	0xFC04C000
-#define MMAP_IACK	0xFC054000
-#define MMAP_I2C	0xFC058000
-#define MMAP_DSPI	0xFC05C000
-#define MMAP_UART0	0xFC060000
-#define MMAP_UART1	0xFC064000
-#define MMAP_UART2	0xFC068000
-#define MMAP_DTMR0	0xFC070000
-#define MMAP_DTMR1	0xFC074000
-#define MMAP_DTMR2	0xFC078000
-#define MMAP_DTMR3	0xFC07C000
-#define MMAP_PIT0	0xFC080000
-#define MMAP_PIT1	0xFC084000
-#define MMAP_PIT2	0xFC088000
-#define MMAP_PIT3	0xFC08C000
-#define MMAP_EPORT	0xFC094000
-#define MMAP_WTM	0xFC098000
-#define MMAP_SBF	0xFC0A0000
-#define MMAP_RCM	0xFC0A0000
-#define MMAP_CCM	0xFC0A0000
-#define MMAP_GPIO	0xFC0A4000
-#define MMAP_PCI	0xFC0A8000
-#define MMAP_PCIARB	0xFC0AC000
-#define MMAP_RNG	0xFC0B4000
-#define MMAP_SDRAM	0xFC0B8000
-#define MMAP_SSI	0xFC0BC000
-#define MMAP_PLL	0xFC0C4000
-#define MMAP_ATA	0x90000000
-#define MMAP_USBHW	0xFC0B0000
-#define MMAP_USBCAPS	0xFC0B0100
-#define MMAP_USBEHCI	0xFC0B0140
-#define MMAP_USBOTG	0xFC0B01A0
-
-#include <asm/coldfire/ata.h>
-#include <asm/coldfire/crossbar.h>
-#include <asm/coldfire/dspi.h>
-#include <asm/coldfire/edma.h>
-#include <asm/coldfire/eport.h>
-#include <asm/coldfire/flexbus.h>
-#include <asm/coldfire/intctrl.h>
-#include <asm/coldfire/ssi.h>
-
-/* Watchdog Timer Modules (WTM) */
-typedef struct wtm {
-	u16 wcr;
-	u16 wmr;
-	u16 wcntr;
-	u16 wsr;
-} wtm_t;
-
-/* Serial Boot Facility (SBF) */
-typedef struct sbf {
-	u8 resv0[0x18];
-	u16 sbfsr;		/* Serial Boot Facility Status Register */
-	u8 resv1[0x6];
-	u16 sbfcr;		/* Serial Boot Facility Control Register */
-} sbf_t;
-
-/* Reset Controller Module (RCM) */
-typedef struct rcm {
-	u8 rcr;
-	u8 rsr;
-} rcm_t;
-
-/* Chip Configuration Module (CCM) */
-typedef struct ccm {
-	u8 ccm_resv0[0x4];
-	u16 ccr;		/* Chip Configuration Register (256 TEPBGA, Read-only) */
-	u8 resv1[0x2];
-	u16 rcon;		/* Reset Configuration (256 TEPBGA, Read-only) */
-	u16 cir;		/* Chip Identification Register (Read-only) */
-	u8 resv2[0x4];
-	u16 misccr;		/* Miscellaneous Control Register */
-	u16 cdr;		/* Clock Divider Register */
-	u16 uocsr;		/* USB On-the-Go Controller Status Register */
-} ccm_t;
-
-/* General Purpose I/O Module (GPIO) */
-typedef struct gpio {
-	u8 podr_fec0h;		/* FEC0 High Port Output Data Register */
-	u8 podr_fec0l;		/* FEC0 Low Port Output Data Register */
-	u8 podr_ssi;		/* SSI Port Output Data Register */
-	u8 podr_fbctl;		/* Flexbus Control Port Output Data Register */
-	u8 podr_be;		/* Flexbus Byte Enable Port Output Data Register */
-	u8 podr_cs;		/* Flexbus Chip-Select Port Output Data Register */
-	u8 podr_dma;		/* DMA Port Output Data Register */
-	u8 podr_feci2c;		/* FEC1 / I2C Port Output Data Register */
-	u8 resv0[0x1];
-	u8 podr_uart;		/* UART Port Output Data Register */
-	u8 podr_dspi;		/* DSPI Port Output Data Register */
-	u8 podr_timer;		/* Timer Port Output Data Register */
-	u8 podr_pci;		/* PCI Port Output Data Register */
-	u8 podr_usb;		/* USB Port Output Data Register */
-	u8 podr_atah;		/* ATA High Port Output Data Register */
-	u8 podr_atal;		/* ATA Low Port Output Data Register */
-	u8 podr_fec1h;		/* FEC1 High Port Output Data Register */
-	u8 podr_fec1l;		/* FEC1 Low Port Output Data Register */
-	u8 resv1[0x2];
-	u8 podr_fbadh;		/* Flexbus AD High Port Output Data Register */
-	u8 podr_fbadmh;		/* Flexbus AD Med-High Port Output Data Register */
-	u8 podr_fbadml;		/* Flexbus AD Med-Low Port Output Data Register */
-	u8 podr_fbadl;		/* Flexbus AD Low Port Output Data Register */
-	u8 pddr_fec0h;		/* FEC0 High Port Data Direction Register */
-	u8 pddr_fec0l;		/* FEC0 Low Port Data Direction Register */
-	u8 pddr_ssi;		/* SSI Port Data Direction Register */
-	u8 pddr_fbctl;		/* Flexbus Control Port Data Direction Register */
-	u8 pddr_be;		/* Flexbus Byte Enable Port Data Direction Register */
-	u8 pddr_cs;		/* Flexbus Chip-Select Port Data Direction Register */
-	u8 pddr_dma;		/* DMA Port Data Direction Register */
-	u8 pddr_feci2c;		/* FEC1 / I2C Port Data Direction Register */
-	u8 resv2[0x1];
-	u8 pddr_uart;		/* UART Port Data Direction Register */
-	u8 pddr_dspi;		/* DSPI Port Data Direction Register */
-	u8 pddr_timer;		/* Timer Port Data Direction Register */
-	u8 pddr_pci;		/* PCI Port Data Direction Register */
-	u8 pddr_usb;		/* USB Port Data Direction Register */
-	u8 pddr_atah;		/* ATA High Port Data Direction Register */
-	u8 pddr_atal;		/* ATA Low Port Data Direction Register */
-	u8 pddr_fec1h;		/* FEC1 High Port Data Direction Register */
-	u8 pddr_fec1l;		/* FEC1 Low Port Data Direction Register */
-	u8 resv3[0x2];
-	u8 pddr_fbadh;		/* Flexbus AD High Port Data Direction Register */
-	u8 pddr_fbadmh;		/* Flexbus AD Med-High Port Data Direction Register */
-	u8 pddr_fbadml;		/* Flexbus AD Med-Low Port Data Direction Register */
-	u8 pddr_fbadl;		/* Flexbus AD Low Port Data Direction Register */
-	u8 ppdsdr_fec0h;	/* FEC0 High Port Pin Data/Set Data Register */
-	u8 ppdsdr_fec0l;	/* FEC0 Low Port Clear Output Data Register */
-	u8 ppdsdr_ssi;		/* SSI Port Pin Data/Set Data Register */
-	u8 ppdsdr_fbctl;	/* Flexbus Control Port Pin Data/Set Data Register */
-	u8 ppdsdr_be;		/* Flexbus Byte Enable Port Pin Data/Set Data Register */
-	u8 ppdsdr_cs;		/* Flexbus Chip-Select Port Pin Data/Set Data Register */
-	u8 ppdsdr_dma;		/* DMA Port Pin Data/Set Data Register */
-	u8 ppdsdr_feci2c;	/* FEC1 / I2C Port Pin Data/Set Data Register */
-	u8 resv4[0x1];
-	u8 ppdsdr_uart;		/* UART Port Pin Data/Set Data Register */
-	u8 ppdsdr_dspi;		/* DSPI Port Pin Data/Set Data Register */
-	u8 ppdsdr_timer;	/* FTimer Port Pin Data/Set Data Register */
-	u8 ppdsdr_pci;		/* PCI Port Pin Data/Set Data Register */
-	u8 ppdsdr_usb;		/* USB Port Pin Data/Set Data Register */
-	u8 ppdsdr_atah;		/* ATA High Port Pin Data/Set Data Register */
-	u8 ppdsdr_atal;		/* ATA Low Port Pin Data/Set Data Register */
-	u8 ppdsdr_fec1h;	/* FEC1 High Port Pin Data/Set Data Register */
-	u8 ppdsdr_fec1l;	/* FEC1 Low Port Pin Data/Set Data Register */
-	u8 resv5[0x2];
-	u8 ppdsdr_fbadh;	/* Flexbus AD High Port Pin Data/Set Data Register */
-	u8 ppdsdr_fbadmh;	/* Flexbus AD Med-High Port Pin Data/Set Data Register */
-	u8 ppdsdr_fbadml;	/* Flexbus AD Med-Low Port Pin Data/Set Data Register */
-	u8 ppdsdr_fbadl;	/* Flexbus AD Low Port Pin Data/Set Data Register */
-	u8 pclrr_fec0h;		/* FEC0 High Port Clear Output Data Register */
-	u8 pclrr_fec0l;		/* FEC0 Low Port Pin Data/Set Data Register */
-	u8 pclrr_ssi;		/* SSI Port Clear Output Data Register */
-	u8 pclrr_fbctl;		/* Flexbus Control Port Clear Output Data Register */
-	u8 pclrr_be;		/* Flexbus Byte Enable Port Clear Output Data Register */
-	u8 pclrr_cs;		/* Flexbus Chip-Select Port Clear Output Data Register */
-	u8 pclrr_dma;		/* DMA Port Clear Output Data Register */
-	u8 pclrr_feci2c;	/* FEC1 / I2C Port Clear Output Data Register */
-	u8 resv6[0x1];
-	u8 pclrr_uart;		/* UART Port Clear Output Data Register */
-	u8 pclrr_dspi;		/* DSPI Port Clear Output Data Register */
-	u8 pclrr_timer;		/* Timer Port Clear Output Data Register */
-	u8 pclrr_pci;		/* PCI Port Clear Output Data Register */
-	u8 pclrr_usb;		/* USB Port Clear Output Data Register */
-	u8 pclrr_atah;		/* ATA High Port Clear Output Data Register */
-	u8 pclrr_atal;		/* ATA Low Port Clear Output Data Register */
-	u8 pclrr_fec1h;		/* FEC1 High Port Clear Output Data Register */
-	u8 pclrr_fec1l;		/* FEC1 Low Port Clear Output Data Register */
-	u8 resv7[0x2];
-	u8 pclrr_fbadh;		/* Flexbus AD High Port Clear Output Data Register */
-	u8 pclrr_fbadmh;	/* Flexbus AD Med-High Port Clear Output Data Register */
-	u8 pclrr_fbadml;	/* Flexbus AD Med-Low Port Clear Output Data Register */
-	u8 pclrr_fbadl;		/* Flexbus AD Low Port Clear Output Data Register */
-	u8 par_fec;		/* FEC Pin Assignment Register */
-	u8 par_dma;		/* DMA Pin Assignment Register */
-	u8 par_fbctl;		/* Flexbus Control Pin Assignment Register */
-	u8 par_dspi;		/* DSPI Pin Assignment Register */
-	u8 par_be;		/* Flexbus Byte-Enable Pin Assignment Register */
-	u8 par_cs;		/* Flexbus Chip-Select Pin Assignment Register */
-	u8 par_timer;		/* Time Pin Assignment Register */
-	u8 par_usb;		/* USB Pin Assignment Register */
-	u8 resv8[0x1];
-	u8 par_uart;		/* UART Pin Assignment Register */
-	u16 par_feci2c;		/* FEC / I2C Pin Assignment Register */
-	u16 par_ssi;		/* SSI Pin Assignment Register */
-	u16 par_ata;		/* ATA Pin Assignment Register */
-	u8 par_irq;		/* IRQ Pin Assignment Register */
-	u8 resv9[0x1];
-	u16 par_pci;		/* PCI Pin Assignment Register */
-	u8 mscr_sdram;		/* SDRAM Mode Select Control Register */
-	u8 mscr_pci;		/* PCI Mode Select Control Register */
-	u8 resv10[0x2];
-	u8 dscr_i2c;		/* I2C Drive Strength Control Register */
-	u8 dscr_flexbus;	/* FLEXBUS Drive Strength Control Register */
-	u8 dscr_fec;		/* FEC Drive Strength Control Register */
-	u8 dscr_uart;		/* UART Drive Strength Control Register */
-	u8 dscr_dspi;		/* DSPI Drive Strength Control Register */
-	u8 dscr_timer;		/* TIMER Drive Strength Control Register */
-	u8 dscr_ssi;		/* SSI Drive Strength Control Register */
-	u8 dscr_dma;		/* DMA Drive Strength Control Register */
-	u8 dscr_debug;		/* DEBUG Drive Strength Control Register */
-	u8 dscr_reset;		/* RESET Drive Strength Control Register */
-	u8 dscr_irq;		/* IRQ Drive Strength Control Register */
-	u8 dscr_usb;		/* USB Drive Strength Control Register */
-	u8 dscr_ata;		/* ATA Drive Strength Control Register */
-} gpio_t;
-
-/* SDRAM Controller (SDRAMC) */
-typedef struct sdramc {
-	u32 sdmr;		/* SDRAM Mode/Extended Mode Register */
-	u32 sdcr;		/* SDRAM Control Register */
-	u32 sdcfg1;		/* SDRAM Configuration Register 1 */
-	u32 sdcfg2;		/* SDRAM Chip Select Register */
-	u8 resv0[0x100];
-	u32 sdcs0;		/* SDRAM Mode/Extended Mode Register */
-	u32 sdcs1;		/* SDRAM Mode/Extended Mode Register */
-} sdramc_t;
-
-/* Phase Locked Loop (PLL) */
-typedef struct pll {
-	u32 pcr;		/* PLL Control Register */
-	u32 psr;		/* PLL Status Register */
-} pll_t;
-
-typedef struct pci {
-	u32 idr;		/* 0x00 Device Id / Vendor Id Register */
-	u32 scr;		/* 0x04 Status / command Register */
-	u32 ccrir;		/* 0x08 Class Code / Revision Id Register */
-	u32 cr1;		/* 0x0c Configuration 1 Register */
-	u32 bar0;		/* 0x10 Base address register 0 Register */
-	u32 bar1;		/* 0x14 Base address register 1 Register */
-	u32 bar2;		/* 0x18 Base address register 2 Register */
-	u32 bar3;		/* 0x1c Base address register 3 Register */
-	u32 bar4;		/* 0x20 Base address register 4 Register */
-	u32 bar5;		/* 0x24 Base address register 5 Register */
-	u32 ccpr;		/* 0x28 Cardbus CIS Pointer Register */
-	u32 sid;		/* 0x2c Subsystem ID / Subsystem Vendor ID Register */
-	u32 erbar;		/* 0x30 Expansion ROM Base Address Register */
-	u32 cpr;		/* 0x34 Capabilities Pointer Register */
-	u32 rsvd1;		/* 0x38 */
-	u32 cr2;		/* 0x3c Configuration Register 2 */
-	u32 rsvd2[8];		/* 0x40 - 0x5f */
-
-	/* General control / status registers */
-	u32 gscr;		/* 0x60 Global Status / Control Register */
-	u32 tbatr0a;		/* 0x64 Target Base Address Translation Register  0 */
-	u32 tbatr1a;		/* 0x68 Target Base Address Translation Register  1 */
-	u32 tcr1;		/* 0x6c Target Control 1 Register */
-	u32 iw0btar;		/* 0x70 Initiator Window 0 Base/Translation addr */
-	u32 iw1btar;		/* 0x74 Initiator Window 1 Base/Translation addr */
-	u32 iw2btar;		/* 0x78 Initiator Window 2 Base/Translation addr */
-	u32 rsvd3;		/* 0x7c */
-	u32 iwcr;		/* 0x80 Initiator Window Configuration Register */
-	u32 icr;		/* 0x84 Initiator Control Register */
-	u32 isr;		/* 0x88 Initiator Status Register */
-	u32 tcr2;		/* 0x8c Target Control 2 Register */
-	u32 tbatr0;		/* 0x90 Target Base Address Translation Register  0 */
-	u32 tbatr1;		/* 0x94 Target Base Address Translation Register  1 */
-	u32 tbatr2;		/* 0x98 Target Base Address Translation Register  2 */
-	u32 tbatr3;		/* 0x9c Target Base Address Translation Register  3 */
-	u32 tbatr4;		/* 0xa0 Target Base Address Translation Register  4 */
-	u32 tbatr5;		/* 0xa4 Target Base Address Translation Register  5 */
-	u32 intr;		/* 0xa8 Interrupt Register */
-	u32 rsvd4[19];		/* 0xac - 0xf7 */
-	u32 car;		/* 0xf8 Configuration Address Register */
-} pci_t;
-
-typedef struct pci_arbiter {
-	/* Pci Arbiter Registers */
-	union {
-		u32 acr;	/* Arbiter Control Register */
-		u32 asr;	/* Arbiter Status Register */
-	};
-} pciarb_t;
-
-/* Register read/write struct */
-typedef struct scm1 {
-	u32 mpr;		/* 0x00 Master Privilege Register */
-	u32 rsvd1[7];
-	u32 pacra;		/* 0x20 Peripheral Access Control Register A */
-	u32 pacrb;		/* 0x24 Peripheral Access Control Register B */
-	u32 pacrc;		/* 0x28 Peripheral Access Control Register C */
-	u32 pacrd;		/* 0x2C Peripheral Access Control Register D */
-	u32 rsvd2[4];
-	u32 pacre;		/* 0x40 Peripheral Access Control Register E */
-	u32 pacrf;		/* 0x44 Peripheral Access Control Register F */
-	u32 pacrg;		/* 0x48 Peripheral Access Control Register G */
-} scm1_t;
-
-typedef struct scm2 {
-	u8 rsvd1[19];		/* 0x00 - 0x12 */
-	u8 wcr;			/* 0x13 */
-	u16 rsvd2;		/* 0x14 - 0x15 */
-	u16 cwcr;		/* 0x16 */
-	u8 rsvd3[3];		/* 0x18 - 0x1A */
-	u8 cwsr;		/* 0x1B */
-	u8 rsvd4[3];		/* 0x1C - 0x1E */
-	u8 scmisr;		/* 0x1F */
-	u32 rsvd5;		/* 0x20 - 0x23 */
-	u8 bcr;			/* 0x24 */
-	u8 rsvd6[74];		/* 0x25 - 0x6F */
-	u32 cfadr;		/* 0x70 */
-	u8 rsvd7;		/* 0x74 */
-	u8 cfier;		/* 0x75 */
-	u8 cfloc;		/* 0x76 */
-	u8 cfatr;		/* 0x77 */
-	u32 rsvd8;		/* 0x78 - 0x7B */
-	u32 cfdtr;		/* 0x7C */
-} scm2_t;
-
-typedef struct rtcex {
-	u32 rsvd1[3];
-	u32 gocu;
-	u32 gocl;
-} rtcex_t;
-#endif				/* __IMMAP_5445X__ */
diff --git a/arch/m68k/include/asm/m5445x.h b/arch/m68k/include/asm/m5445x.h
deleted file mode 100644
index 498c2255f6..0000000000
--- a/arch/m68k/include/asm/m5445x.h
+++ /dev/null
@@ -1,888 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * MCF5445x Internal Memory Map
- *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-#ifndef __MCF5445X__
-#define __MCF5445X__
-
-/*********************************************************************
-* Interrupt Controller (INTC)
-*********************************************************************/
-#define INT0_LO_RSVD0			(0)
-#define INT0_LO_EPORT1			(1)
-#define INT0_LO_EPORT2			(2)
-#define INT0_LO_EPORT3			(3)
-#define INT0_LO_EPORT4			(4)
-#define INT0_LO_EPORT5			(5)
-#define INT0_LO_EPORT6			(6)
-#define INT0_LO_EPORT7			(7)
-#define INT0_LO_EDMA_00			(8)
-#define INT0_LO_EDMA_01			(9)
-#define INT0_LO_EDMA_02			(10)
-#define INT0_LO_EDMA_03			(11)
-#define INT0_LO_EDMA_04			(12)
-#define INT0_LO_EDMA_05			(13)
-#define INT0_LO_EDMA_06			(14)
-#define INT0_LO_EDMA_07			(15)
-#define INT0_LO_EDMA_08			(16)
-#define INT0_LO_EDMA_09			(17)
-#define INT0_LO_EDMA_10			(18)
-#define INT0_LO_EDMA_11			(19)
-#define INT0_LO_EDMA_12			(20)
-#define INT0_LO_EDMA_13			(21)
-#define INT0_LO_EDMA_14			(22)
-#define INT0_LO_EDMA_15			(23)
-#define INT0_LO_EDMA_ERR		(24)
-#define INT0_LO_SCM			(25)
-#define INT0_LO_UART0			(26)
-#define INT0_LO_UART1			(27)
-#define INT0_LO_UART2			(28)
-#define INT0_LO_RSVD1			(29)
-#define INT0_LO_I2C			(30)
-#define INT0_LO_QSPI			(31)
-#define INT0_HI_DTMR0			(32)
-#define INT0_HI_DTMR1			(33)
-#define INT0_HI_DTMR2			(34)
-#define INT0_HI_DTMR3			(35)
-#define INT0_HI_FEC0_TXF		(36)
-#define INT0_HI_FEC0_TXB		(37)
-#define INT0_HI_FEC0_UN			(38)
-#define INT0_HI_FEC0_RL			(39)
-#define INT0_HI_FEC0_RXF		(40)
-#define INT0_HI_FEC0_RXB		(41)
-#define INT0_HI_FEC0_MII		(42)
-#define INT0_HI_FEC0_LC			(43)
-#define INT0_HI_FEC0_HBERR		(44)
-#define INT0_HI_FEC0_GRA		(45)
-#define INT0_HI_FEC0_EBERR		(46)
-#define INT0_HI_FEC0_BABT		(47)
-#define INT0_HI_FEC0_BABR		(48)
-#define INT0_HI_FEC1_TXF		(49)
-#define INT0_HI_FEC1_TXB		(50)
-#define INT0_HI_FEC1_UN			(51)
-#define INT0_HI_FEC1_RL			(52)
-#define INT0_HI_FEC1_RXF		(53)
-#define INT0_HI_FEC1_RXB		(54)
-#define INT0_HI_FEC1_MII		(55)
-#define INT0_HI_FEC1_LC			(56)
-#define INT0_HI_FEC1_HBERR		(57)
-#define INT0_HI_FEC1_GRA		(58)
-#define INT0_HI_FEC1_EBERR		(59)
-#define INT0_HI_FEC1_BABT		(60)
-#define INT0_HI_FEC1_BABR		(61)
-#define INT0_HI_SCMIR			(62)
-#define INT0_HI_RTC_ISR			(63)
-
-#define INT1_HI_DSPI_EOQF		(33)
-#define INT1_HI_DSPI_TFFF		(34)
-#define INT1_HI_DSPI_TCF		(35)
-#define INT1_HI_DSPI_TFUF		(36)
-#define INT1_HI_DSPI_RFDF		(37)
-#define INT1_HI_DSPI_RFOF		(38)
-#define INT1_HI_DSPI_RFOF_TFUF		(39)
-#define INT1_HI_RNG_EI			(40)
-#define INT1_HI_PIT0_PIF		(43)
-#define INT1_HI_PIT1_PIF		(44)
-#define INT1_HI_PIT2_PIF		(45)
-#define INT1_HI_PIT3_PIF		(46)
-#define INT1_HI_USBOTG_USBSTS		(47)
-#define INT1_HI_SSI_ISR			(49)
-#define INT1_HI_CCM_UOCSR		(53)
-#define INT1_HI_ATA_ISR			(54)
-#define INT1_HI_PCI_SCR			(55)
-#define INT1_HI_PCI_ASR			(56)
-#define INT1_HI_PLL_LOCKS		(57)
-
-/*********************************************************************
-* Watchdog Timer Modules (WTM)
-*********************************************************************/
-
-/* Bit definitions and macros for WCR */
-#define WTM_WCR_EN			(0x0001)
-#define WTM_WCR_HALTED			(0x0002)
-#define WTM_WCR_DOZE			(0x0004)
-#define WTM_WCR_WAIT			(0x0008)
-
-/*********************************************************************
-* Serial Boot Facility (SBF)
-*********************************************************************/
-
-/* Bit definitions and macros for SBFCR */
-#define SBF_SBFCR_BLDIV(x)		(((x)&0x000F))	/* Boot loader clock divider */
-#define SBF_SBFCR_FR			(0x0010)	/* Fast read */
-
-/*********************************************************************
-* Reset Controller Module (RCM)
-*********************************************************************/
-
-/* Bit definitions and macros for RCR */
-#define RCM_RCR_FRCRSTOUT		(0x40)
-#define RCM_RCR_SOFTRST			(0x80)
-
-/* Bit definitions and macros for RSR */
-#define RCM_RSR_LOL			(0x01)
-#define RCM_RSR_WDR_CORE		(0x02)
-#define RCM_RSR_EXT			(0x04)
-#define RCM_RSR_POR			(0x08)
-#define RCM_RSR_SOFT			(0x20)
-
-/*********************************************************************
-* Chip Configuration Module (CCM)
-*********************************************************************/
-
-/* Bit definitions and macros for CCR_360 */
-#define CCM_CCR_360_PLLMULT2(x)		(((x)&0x0003))	/* 2-Bit PLL clock mode */
-#define CCM_CCR_360_PCISLEW		(0x0004)	/* PCI pad slew rate mode */
-#define CCM_CCR_360_PCIMODE		(0x0008)	/* PCI host/agent mode */
-#define CCM_CCR_360_PLLMODE		(0x0010)	/* PLL Mode */
-#define CCM_CCR_360_FBCONFIG(x)		(((x)&0x0007)<<5)	/* Flexbus/PCI port size configuration */
-#define CCM_CCR_360_PLLMULT3(x)		(((x)&0x0007))	/* 3-Bit PLL Clock Mode */
-#define CCM_CCR_360_OSCMODE		(0x0008)	/* Oscillator Clock Mode */
-#define CCM_CCR_360_FBCONFIG_MASK	(0x00E0)
-#define CCM_CCR_360_PLLMULT2_MASK	(0x0003)
-#define CCM_CCR_360_PLLMULT3_MASK	(0x0007)
-#define CCM_CCR_360_FBCONFIG_NM_NP_32	(0x0000)
-#define CCM_CCR_360_FBCONFIG_NM_NP_8	(0x0020)
-#define CCM_CCR_360_FBCONFIG_NM_NP_16	(0x0040)
-#define CCM_CCR_360_FBCONFIG_M_P_16	(0x0060)
-#define CCM_CCR_360_FBCONFIG_M_NP_32	(0x0080)
-#define CCM_CCR_360_FBCONFIG_M_NP_8	(0x00A0)
-#define CCM_CCR_360_FBCONFIG_M_NP_16	(0x00C0)
-#define CCM_CCR_360_FBCONFIG_M_P_8	(0x00E0)
-#define CCM_CCR_360_PLLMULT2_12X	(0x0000)
-#define CCM_CCR_360_PLLMULT2_6X		(0x0001)
-#define CCM_CCR_360_PLLMULT2_16X	(0x0002)
-#define CCM_CCR_360_PLLMULT2_8X		(0x0003)
-#define CCM_CCR_360_PLLMULT3_20X	(0x0000)
-#define CCM_CCR_360_PLLMULT3_10X	(0x0001)
-#define CCM_CCR_360_PLLMULT3_24X	(0x0002)
-#define CCM_CCR_360_PLLMULT3_18X	(0x0003)
-#define CCM_CCR_360_PLLMULT3_12X	(0x0004)
-#define CCM_CCR_360_PLLMULT3_6X		(0x0005)
-#define CCM_CCR_360_PLLMULT3_16X	(0x0006)
-#define CCM_CCR_360_PLLMULT3_8X		(0x0007)
-
-/* Bit definitions and macros for CCR_256 */
-#define CCM_CCR_256_PLLMULT3(x)		(((x)&0x0007))	/* 3-Bit PLL clock mode */
-#define CCM_CCR_256_OSCMODE		(0x0008)	/* Oscillator clock mode */
-#define CCM_CCR_256_PLLMODE		(0x0010)	/* PLL Mode */
-#define CCM_CCR_256_FBCONFIG(x)		(((x)&0x0007)<<5)	/* Flexbus/PCI port size configuration */
-#define CCM_CCR_256_FBCONFIG_MASK	(0x00E0)
-#define CCM_CCR_256_FBCONFIG_NM_32	(0x0000)
-#define CCM_CCR_256_FBCONFIG_NM_8	(0x0020)
-#define CCM_CCR_256_FBCONFIG_NM_16	(0x0040)
-#define CCM_CCR_256_FBCONFIG_M_32	(0x0080)
-#define CCM_CCR_256_FBCONFIG_M_8	(0x00A0)
-#define CCM_CCR_256_FBCONFIG_M_16	(0x00C0)
-#define CCM_CCR_256_PLLMULT3_MASK	(0x0007)
-#define CCM_CCR_256_PLLMULT3_20X	(0x0000)
-#define CCM_CCR_256_PLLMULT3_10X	(0x0001)
-#define CCM_CCR_256_PLLMULT3_24X	(0x0002)
-#define CCM_CCR_256_PLLMULT3_18X	(0x0003)
-#define CCM_CCR_256_PLLMULT3_12X	(0x0004)
-#define CCM_CCR_256_PLLMULT3_6X		(0x0005)
-#define CCM_CCR_256_PLLMULT3_16X	(0x0006)
-#define CCM_CCR_256_PLLMULT3_8X		(0x0007)
-
-/* Bit definitions and macros for RCON_360 */
-#define CCM_RCON_360_PLLMULT(x)		(((x)&0x0003))	/* PLL clock mode */
-#define CCM_RCON_360_PCISLEW		(0x0004)	/* PCI pad slew rate mode */
-#define CCM_RCON_360_PCIMODE		(0x0008)	/* PCI host/agent mode */
-#define CCM_RCON_360_PLLMODE		(0x0010)	/* PLL Mode */
-#define CCM_RCON_360_FBCONFIG(x)	(((x)&0x0007)<<5)	/* Flexbus/PCI port size configuration */
-
-/* Bit definitions and macros for RCON_256 */
-#define CCM_RCON_256_PLLMULT(x)		(((x)&0x0007))	/* PLL clock mode */
-#define CCM_RCON_256_OSCMODE		(0x0008)	/* Oscillator clock mode */
-#define CCM_RCON_256_PLLMODE		(0x0010)	/* PLL Mode */
-#define CCM_RCON_256_FBCONFIG(x)	(((x)&0x0007)<<5)	/* Flexbus/PCI port size configuration */
-
-/* Bit definitions and macros for CIR */
-#define CCM_CIR_PRN(x)			(((x)&0x003F))	/* Part revision number */
-#define CCM_CIR_PIN(x)			(((x)&0x03FF)<<6)	/* Part identification number */
-#define CCM_CIR_PIN_MASK		(0xFFC0)
-#define CCM_CIR_PRN_MASK		(0x003F)
-#define CCM_CIR_PIN_MCF54450		(0x4F<<6)
-#define CCM_CIR_PIN_MCF54451		(0x4D<<6)
-#define CCM_CIR_PIN_MCF54452		(0x4B<<6)
-#define CCM_CIR_PIN_MCF54453		(0x49<<6)
-#define CCM_CIR_PIN_MCF54454		(0x4A<<6)
-#define CCM_CIR_PIN_MCF54455		(0x48<<6)
-
-/* Bit definitions and macros for MISCCR */
-#define CCM_MISCCR_USBSRC		(0x0001)	/* USB clock source */
-#define CCM_MISCCR_USBOC		(0x0002)	/* USB VBUS over-current sense polarity */
-#define CCM_MISCCR_USBPUE		(0x0004)	/* USB transceiver pull-up enable */
-#define CCM_MISCCR_SSISRC		(0x0010)	/* SSI clock source */
-#define CCM_MISCCR_TIMDMA		(0x0020)	/* Timer DMA mux selection */
-#define CCM_MISCCR_SSIPUS		(0x0040)	/* SSI RXD/TXD pull select */
-#define CCM_MISCCR_SSIPUE		(0x0080)	/* SSI RXD/TXD pull enable */
-#define CCM_MISCCR_BMT(x)		(((x)&0x0007)<<8)	/* Bus monitor timing field */
-#define CCM_MISCCR_BME			(0x0800)	/* Bus monitor external enable bit */
-#define CCM_MISCCR_LIMP			(0x1000)	/* Limp mode enable */
-#define CCM_MISCCR_BMT_65536		(0)
-#define CCM_MISCCR_BMT_32768		(1)
-#define CCM_MISCCR_BMT_16384		(2)
-#define CCM_MISCCR_BMT_8192		(3)
-#define CCM_MISCCR_BMT_4096		(4)
-#define CCM_MISCCR_BMT_2048		(5)
-#define CCM_MISCCR_BMT_1024		(6)
-#define CCM_MISCCR_BMT_512		(7)
-#define CCM_MISCCR_SSIPUS_UP		(1)
-#define CCM_MISCCR_SSIPUS_DOWN		(0)
-#define CCM_MISCCR_TIMDMA_TIM		(1)
-#define CCM_MISCCR_TIMDMA_SSI		(0)
-#define CCM_MISCCR_SSISRC_CLKIN		(0)
-#define CCM_MISCCR_SSISRC_PLL		(1)
-#define CCM_MISCCR_USBOC_ACTHI		(0)
-#define CCM_MISCCR_USBOV_ACTLO		(1)
-#define CCM_MISCCR_USBSRC_CLKIN		(0)
-#define CCM_MISCCR_USBSRC_PLL		(1)
-
-/* Bit definitions and macros for CDR */
-#define CCM_CDR_SSIDIV(x)		(((x)&0x00FF))	/* SSI oversampling clock divider */
-#define CCM_CDR_LPDIV(x)		(((x)&0x000F)<<8)	/* Low power clock divider */
-
-/* Bit definitions and macros for UOCSR */
-#define CCM_UOCSR_XPDE			(0x0001)	/* On-chip transceiver pull-down enable */
-#define CCM_UOCSR_UOMIE			(0x0002)	/* USB OTG misc interrupt enable */
-#define CCM_UOCSR_WKUP			(0x0004)	/* USB OTG controller wake-up event */
-#define CCM_UOCSR_PWRFLT		(0x0008)	/* VBUS power fault */
-#define CCM_UOCSR_SEND			(0x0010)	/* Session end */
-#define CCM_UOCSR_VVLD			(0x0020)	/* VBUS valid indicator */
-#define CCM_UOCSR_BVLD			(0x0040)	/* B-peripheral valid indicator */
-#define CCM_UOCSR_AVLD			(0x0080)	/* A-peripheral valid indicator */
-#define CCM_UOCSR_DPPU			(0x0100)	/* D+ pull-up for FS enabled (read-only) */
-#define CCM_UOCSR_DCR_VBUS		(0x0200)	/* VBUS discharge resistor enabled (read-only) */
-#define CCM_UOCSR_CRG_VBUS		(0x0400)	/* VBUS charge resistor enabled (read-only) */
-#define CCM_UOCSR_DMPD			(0x1000)	/* D- 15Kohm pull-down (read-only) */
-#define CCM_UOCSR_DPPD			(0x2000)	/* D+ 15Kohm pull-down (read-only) */
-
-/*********************************************************************
-* General Purpose I/O Module (GPIO)
-*********************************************************************/
-
-/* Bit definitions and macros for PAR_FEC */
-#define GPIO_PAR_FEC_FEC0(x)		(((x)&0x07))
-#define GPIO_PAR_FEC_FEC1(x)		(((x)&0x07)<<4)
-#define GPIO_PAR_FEC_FEC1_UNMASK	(0x8F)
-#define GPIO_PAR_FEC_FEC1_MII		(0x70)
-#define GPIO_PAR_FEC_FEC1_RMII_GPIO	(0x30)
-#define GPIO_PAR_FEC_FEC1_RMII_ATA	(0x20)
-#define GPIO_PAR_FEC_FEC1_ATA		(0x10)
-#define GPIO_PAR_FEC_FEC1_GPIO		(0x00)
-#define GPIO_PAR_FEC_FEC0_UNMASK	(0xF8)
-#define GPIO_PAR_FEC_FEC0_MII		(0x07)
-#define GPIO_PAR_FEC_FEC0_RMII_GPIO	(0x03)
-#define GPIO_PAR_FEC_FEC0_RMII_ULPI	(0x02)
-#define GPIO_PAR_FEC_FEC0_ULPI		(0x01)
-#define GPIO_PAR_FEC_FEC0_GPIO		(0x00)
-
-/* Bit definitions and macros for PAR_DMA */
-#define GPIO_PAR_DMA_DREQ0		(0x01)
-#define GPIO_PAR_DMA_DACK0(x)		(((x)&0x03)<<2)
-#define GPIO_PAR_DMA_DREQ1(x)		(((x)&0x03)<<4)
-#define GPIO_PAR_DMA_DACK1(x)		(((x)&0x03)<<6)
-#define GPIO_PAR_DMA_DACK1_UNMASK	(0x3F)
-#define GPIO_PAR_DMA_DACK1_DACK1	(0xC0)
-#define GPIO_PAR_DMA_DACK1_ULPI_DIR	(0x40)
-#define GPIO_PAR_DMA_DACK1_GPIO		(0x00)
-#define GPIO_PAR_DMA_DREQ1_UNMASK	(0xCF)
-#define GPIO_PAR_DMA_DREQ1_DREQ1	(0x30)
-#define GPIO_PAR_DMA_DREQ1_USB_CLKIN	(0x10)
-#define GPIO_PAR_DMA_DREQ1_GPIO		(0x00)
-#define GPIO_PAR_DMA_DACK0_UNMASK	(0xF3)
-#define GPIO_PAR_DMA_DACK0_DACK1	(0x0C)
-#define GPIO_PAR_DMA_DACK0_PCS3		(0x08)
-#define GPIO_PAR_DMA_DACK0_ULPI_DIR	(0x04)
-#define GPIO_PAR_DMA_DACK0_GPIO		(0x00)
-#define GPIO_PAR_DMA_DREQ0_DREQ0	(0x01)
-#define GPIO_PAR_DMA_DREQ0_GPIO		(0x00)
-
-/* Bit definitions and macros for PAR_FBCTL */
-#define GPIO_PAR_FBCTL_TS(x)		(((x)&0x03)<<3)
-#define GPIO_PAR_FBCTL_RW		(0x20)
-#define GPIO_PAR_FBCTL_TA		(0x40)
-#define GPIO_PAR_FBCTL_OE		(0x80)
-#define GPIO_PAR_FBCTL_OE_OE		(0x80)
-#define GPIO_PAR_FBCTL_OE_GPIO		(0x00)
-#define GPIO_PAR_FBCTL_TA_TA		(0x40)
-#define GPIO_PAR_FBCTL_TA_GPIO		(0x00)
-#define GPIO_PAR_FBCTL_RW_RW		(0x20)
-#define GPIO_PAR_FBCTL_RW_GPIO		(0x00)
-#define GPIO_PAR_FBCTL_TS_UNMASK	(0xE7)
-#define GPIO_PAR_FBCTL_TS_TS		(0x18)
-#define GPIO_PAR_FBCTL_TS_ALE		(0x10)
-#define GPIO_PAR_FBCTL_TS_TBST		(0x08)
-#define GPIO_PAR_FBCTL_TS_GPIO		(0x80)
-
-/* Bit definitions and macros for PAR_DSPI */
-#define GPIO_PAR_DSPI_SCK		(0x01)
-#define GPIO_PAR_DSPI_SOUT		(0x02)
-#define GPIO_PAR_DSPI_SIN		(0x04)
-#define GPIO_PAR_DSPI_PCS0		(0x08)
-#define GPIO_PAR_DSPI_PCS1		(0x10)
-#define GPIO_PAR_DSPI_PCS2		(0x20)
-#define GPIO_PAR_DSPI_PCS5		(0x40)
-#define GPIO_PAR_DSPI_PCS5_PCS5		(0x40)
-#define GPIO_PAR_DSPI_PCS5_GPIO		(0x00)
-#define GPIO_PAR_DSPI_PCS2_PCS2		(0x20)
-#define GPIO_PAR_DSPI_PCS2_GPIO		(0x00)
-#define GPIO_PAR_DSPI_PCS1_PCS1		(0x10)
-#define GPIO_PAR_DSPI_PCS1_GPIO		(0x00)
-#define GPIO_PAR_DSPI_PCS0_PCS0		(0x08)
-#define GPIO_PAR_DSPI_PCS0_GPIO		(0x00)
-#define GPIO_PAR_DSPI_SIN_SIN		(0x04)
-#define GPIO_PAR_DSPI_SIN_GPIO		(0x00)
-#define GPIO_PAR_DSPI_SOUT_SOUT		(0x02)
-#define GPIO_PAR_DSPI_SOUT_GPIO		(0x00)
-#define GPIO_PAR_DSPI_SCK_SCK		(0x01)
-#define GPIO_PAR_DSPI_SCK_GPIO		(0x00)
-
-/* Bit definitions and macros for PAR_BE */
-#define GPIO_PAR_BE_BS0			(0x01)
-#define GPIO_PAR_BE_BS1			(0x04)
-#define GPIO_PAR_BE_BS2(x)		(((x)&0x03)<<4)
-#define GPIO_PAR_BE_BS3(x)		(((x)&0x03)<<6)
-#define GPIO_PAR_BE_BE3_UNMASK		(0x3F)
-#define GPIO_PAR_BE_BE3_BE3		(0xC0)
-#define GPIO_PAR_BE_BE3_TSIZ1		(0x80)
-#define GPIO_PAR_BE_BE3_GPIO		(0x00)
-#define GPIO_PAR_BE_BE2_UNMASK		(0xCF)
-#define GPIO_PAR_BE_BE2_BE2		(0x30)
-#define GPIO_PAR_BE_BE2_TSIZ0		(0x20)
-#define GPIO_PAR_BE_BE2_GPIO		(0x00)
-#define GPIO_PAR_BE_BE1_BE1		(0x04)
-#define GPIO_PAR_BE_BE1_GPIO		(0x00)
-#define GPIO_PAR_BE_BE0_BE0		(0x01)
-#define GPIO_PAR_BE_BE0_GPIO		(0x00)
-
-/* Bit definitions and macros for PAR_CS */
-#define GPIO_PAR_CS_CS1			(0x02)
-#define GPIO_PAR_CS_CS2			(0x04)
-#define GPIO_PAR_CS_CS3			(0x08)
-#define GPIO_PAR_CS_CS3_CS3		(0x08)
-#define GPIO_PAR_CS_CS3_GPIO		(0x00)
-#define GPIO_PAR_CS_CS2_CS2		(0x04)
-#define GPIO_PAR_CS_CS2_GPIO		(0x00)
-#define GPIO_PAR_CS_CS1_CS1		(0x02)
-#define GPIO_PAR_CS_CS1_GPIO		(0x00)
-
-/* Bit definitions and macros for PAR_TIMER */
-#define GPIO_PAR_TIMER_T0IN(x)		(((x)&0x03))
-#define GPIO_PAR_TIMER_T1IN(x)		(((x)&0x03)<<2)
-#define GPIO_PAR_TIMER_T2IN(x)		(((x)&0x03)<<4)
-#define GPIO_PAR_TIMER_T3IN(x)		(((x)&0x03)<<6)
-#define GPIO_PAR_TIMER_T3IN_UNMASK	(0x3F)
-#define GPIO_PAR_TIMER_T3IN_T3IN	(0xC0)
-#define GPIO_PAR_TIMER_T3IN_T3OUT	(0x80)
-#define GPIO_PAR_TIMER_T3IN_U2RXD	(0x40)
-#define GPIO_PAR_TIMER_T3IN_GPIO	(0x00)
-#define GPIO_PAR_TIMER_T2IN_UNMASK	(0xCF)
-#define GPIO_PAR_TIMER_T2IN_T2IN	(0x30)
-#define GPIO_PAR_TIMER_T2IN_T2OUT	(0x20)
-#define GPIO_PAR_TIMER_T2IN_U2TXD	(0x10)
-#define GPIO_PAR_TIMER_T2IN_GPIO	(0x00)
-#define GPIO_PAR_TIMER_T1IN_UNMASK	(0xF3)
-#define GPIO_PAR_TIMER_T1IN_T1IN	(0x0C)
-#define GPIO_PAR_TIMER_T1IN_T1OUT	(0x08)
-#define GPIO_PAR_TIMER_T1IN_U2CTS	(0x04)
-#define GPIO_PAR_TIMER_T1IN_GPIO	(0x00)
-#define GPIO_PAR_TIMER_T0IN_UNMASK	(0xFC)
-#define GPIO_PAR_TIMER_T0IN_T0IN	(0x03)
-#define GPIO_PAR_TIMER_T0IN_T0OUT	(0x02)
-#define GPIO_PAR_TIMER_T0IN_U2RTS	(0x01)
-#define GPIO_PAR_TIMER_T0IN_GPIO	(0x00)
-
-/* Bit definitions and macros for PAR_USB */
-#define GPIO_PAR_USB_VBUSOC(x)		(((x)&0x03))
-#define GPIO_PAR_USB_VBUSEN(x)		(((x)&0x03)<<2)
-#define GPIO_PAR_USB_VBUSEN_UNMASK	(0xF3)
-#define GPIO_PAR_USB_VBUSEN_VBUSEN	(0x0C)
-#define GPIO_PAR_USB_VBUSEN_USBPULLUP	(0x08)
-#define GPIO_PAR_USB_VBUSEN_ULPI_NXT	(0x04)
-#define GPIO_PAR_USB_VBUSEN_GPIO	(0x00)
-#define GPIO_PAR_USB_VBUSOC_UNMASK	(0xFC)
-#define GPIO_PAR_USB_VBUSOC_VBUSOC	(0x03)
-#define GPIO_PAR_USB_VBUSOC_ULPI_STP	(0x01)
-#define GPIO_PAR_USB_VBUSOC_GPIO	(0x00)
-
-/* Bit definitions and macros for PAR_UART */
-#define GPIO_PAR_UART_U0TXD		(0x01)
-#define GPIO_PAR_UART_U0RXD		(0x02)
-#define GPIO_PAR_UART_U0RTS		(0x04)
-#define GPIO_PAR_UART_U0CTS		(0x08)
-#define GPIO_PAR_UART_U1TXD		(0x10)
-#define GPIO_PAR_UART_U1RXD		(0x20)
-#define GPIO_PAR_UART_U1RTS		(0x40)
-#define GPIO_PAR_UART_U1CTS		(0x80)
-#define GPIO_PAR_UART_U1CTS_U1CTS	(0x80)
-#define GPIO_PAR_UART_U1CTS_GPIO	(0x00)
-#define GPIO_PAR_UART_U1RTS_U1RTS	(0x40)
-#define GPIO_PAR_UART_U1RTS_GPIO	(0x00)
-#define GPIO_PAR_UART_U1RXD_U1RXD	(0x20)
-#define GPIO_PAR_UART_U1RXD_GPIO	(0x00)
-#define GPIO_PAR_UART_U1TXD_U1TXD	(0x10)
-#define GPIO_PAR_UART_U1TXD_GPIO	(0x00)
-#define GPIO_PAR_UART_U0CTS_U0CTS	(0x08)
-#define GPIO_PAR_UART_U0CTS_GPIO	(0x00)
-#define GPIO_PAR_UART_U0RTS_U0RTS	(0x04)
-#define GPIO_PAR_UART_U0RTS_GPIO	(0x00)
-#define GPIO_PAR_UART_U0RXD_U0RXD	(0x02)
-#define GPIO_PAR_UART_U0RXD_GPIO	(0x00)
-#define GPIO_PAR_UART_U0TXD_U0TXD	(0x01)
-#define GPIO_PAR_UART_U0TXD_GPIO	(0x00)
-
-/* Bit definitions and macros for PAR_FECI2C */
-#define GPIO_PAR_FECI2C_SDA(x)		(((x)&0x0003))
-#define GPIO_PAR_FECI2C_SCL(x)		(((x)&0x0003)<<2)
-#define GPIO_PAR_FECI2C_MDIO0		(0x0010)
-#define GPIO_PAR_FECI2C_MDC0		(0x0040)
-#define GPIO_PAR_FECI2C_MDIO1(x)	(((x)&0x0003)<<8)
-#define GPIO_PAR_FECI2C_MDC1(x)		(((x)&0x0003)<<10)
-#define GPIO_PAR_FECI2C_MDC1_UNMASK	(0xF3FF)
-#define GPIO_PAR_FECI2C_MDC1_MDC1	(0x0C00)
-#define GPIO_PAR_FECI2C_MDC1_ATA_DIOR	(0x0800)
-#define GPIO_PAR_FECI2C_MDC1_GPIO	(0x0000)
-#define GPIO_PAR_FECI2C_MDIO1_UNMASK	(0xFCFF)
-#define GPIO_PAR_FECI2C_MDIO1_MDIO1	(0x0300)
-#define GPIO_PAR_FECI2C_MDIO1_ATA_DIOW	(0x0200)
-#define GPIO_PAR_FECI2C_MDIO1_GPIO	(0x0000)
-#define GPIO_PAR_FECI2C_MDC0_MDC0	(0x0040)
-#define GPIO_PAR_FECI2C_MDC0_GPIO	(0x0000)
-#define GPIO_PAR_FECI2C_MDIO0_MDIO0	(0x0010)
-#define GPIO_PAR_FECI2C_MDIO0_GPIO	(0x0000)
-#define GPIO_PAR_FECI2C_SCL_UNMASK	(0xFFF3)
-#define GPIO_PAR_FECI2C_SCL_SCL		(0x000C)
-#define GPIO_PAR_FECI2C_SCL_U2TXD	(0x0004)
-#define GPIO_PAR_FECI2C_SCL_GPIO	(0x0000)
-#define GPIO_PAR_FECI2C_SDA_UNMASK	(0xFFFC)
-#define GPIO_PAR_FECI2C_SDA_SDA		(0x0003)
-#define GPIO_PAR_FECI2C_SDA_U2RXD	(0x0001)
-#define GPIO_PAR_FECI2C_SDA_GPIO	(0x0000)
-
-/* Bit definitions and macros for PAR_SSI */
-#define GPIO_PAR_SSI_MCLK		(0x0001)
-#define GPIO_PAR_SSI_STXD(x)		(((x)&0x0003)<<2)
-#define GPIO_PAR_SSI_SRXD(x)		(((x)&0x0003)<<4)
-#define GPIO_PAR_SSI_FS(x)		(((x)&0x0003)<<6)
-#define GPIO_PAR_SSI_BCLK(x)		(((x)&0x0003)<<8)
-#define GPIO_PAR_SSI_BCLK_UNMASK	(0xFCFF)
-#define GPIO_PAR_SSI_BCLK_BCLK		(0x0300)
-#define GPIO_PAR_SSI_BCLK_U1CTS		(0x0200)
-#define GPIO_PAR_SSI_BCLK_GPIO		(0x0000)
-#define GPIO_PAR_SSI_FS_UNMASK		(0xFF3F)
-#define GPIO_PAR_SSI_FS_FS		(0x00C0)
-#define GPIO_PAR_SSI_FS_U1RTS		(0x0080)
-#define GPIO_PAR_SSI_FS_GPIO		(0x0000)
-#define GPIO_PAR_SSI_SRXD_UNMASK	(0xFFCF)
-#define GPIO_PAR_SSI_SRXD_SRXD		(0x0030)
-#define GPIO_PAR_SSI_SRXD_U1RXD		(0x0020)
-#define GPIO_PAR_SSI_SRXD_GPIO		(0x0000)
-#define GPIO_PAR_SSI_STXD_UNMASK	(0xFFF3)
-#define GPIO_PAR_SSI_STXD_STXD		(0x000C)
-#define GPIO_PAR_SSI_STXD_U1TXD		(0x0008)
-#define GPIO_PAR_SSI_STXD_GPIO		(0x0000)
-#define GPIO_PAR_SSI_MCLK_MCLK		(0x0001)
-#define GPIO_PAR_SSI_MCLK_GPIO		(0x0000)
-
-/* Bit definitions and macros for PAR_ATA */
-#define GPIO_PAR_ATA_IORDY		(0x0001)
-#define GPIO_PAR_ATA_DMARQ		(0x0002)
-#define GPIO_PAR_ATA_RESET		(0x0004)
-#define GPIO_PAR_ATA_DA0		(0x0020)
-#define GPIO_PAR_ATA_DA1		(0x0040)
-#define GPIO_PAR_ATA_DA2		(0x0080)
-#define GPIO_PAR_ATA_CS0		(0x0100)
-#define GPIO_PAR_ATA_CS1		(0x0200)
-#define GPIO_PAR_ATA_BUFEN		(0x0400)
-#define GPIO_PAR_ATA_BUFEN_BUFEN	(0x0400)
-#define GPIO_PAR_ATA_BUFEN_GPIO		(0x0000)
-#define GPIO_PAR_ATA_CS1_CS1		(0x0200)
-#define GPIO_PAR_ATA_CS1_GPIO		(0x0000)
-#define GPIO_PAR_ATA_CS0_CS0		(0x0100)
-#define GPIO_PAR_ATA_CS0_GPIO		(0x0000)
-#define GPIO_PAR_ATA_DA2_DA2		(0x0080)
-#define GPIO_PAR_ATA_DA2_GPIO		(0x0000)
-#define GPIO_PAR_ATA_DA1_DA1		(0x0040)
-#define GPIO_PAR_ATA_DA1_GPIO		(0x0000)
-#define GPIO_PAR_ATA_DA0_DA0		(0x0020)
-#define GPIO_PAR_ATA_DA0_GPIO		(0x0000)
-#define GPIO_PAR_ATA_RESET_RESET	(0x0004)
-#define GPIO_PAR_ATA_RESET_GPIO		(0x0000)
-#define GPIO_PAR_ATA_DMARQ_DMARQ	(0x0002)
-#define GPIO_PAR_ATA_DMARQ_GPIO		(0x0000)
-#define GPIO_PAR_ATA_IORDY_IORDY	(0x0001)
-#define GPIO_PAR_ATA_IORDY_GPIO		(0x0000)
-
-/* Bit definitions and macros for PAR_IRQ */
-#define GPIO_PAR_IRQ_IRQ1		(0x02)
-#define GPIO_PAR_IRQ_IRQ4		(0x10)
-#define GPIO_PAR_IRQ_IRQ4_IRQ4		(0x10)
-#define GPIO_PAR_IRQ_IRQ4_GPIO		(0x00)
-#define GPIO_PAR_IRQ_IRQ1_IRQ1		(0x02)
-#define GPIO_PAR_IRQ_IRQ1_GPIO		(0x00)
-
-/* Bit definitions and macros for PAR_PCI */
-#define GPIO_PAR_PCI_REQ0		(0x0001)
-#define GPIO_PAR_PCI_REQ1		(0x0004)
-#define GPIO_PAR_PCI_REQ2		(0x0010)
-#define GPIO_PAR_PCI_REQ3(x)		(((x)&0x0003)<<6)
-#define GPIO_PAR_PCI_GNT0		(0x0100)
-#define GPIO_PAR_PCI_GNT1		(0x0400)
-#define GPIO_PAR_PCI_GNT2		(0x1000)
-#define GPIO_PAR_PCI_GNT3(x)		(((x)&0x0003)<<14)
-#define GPIO_PAR_PCI_GNT3_UNMASK	(0x3FFF)
-#define GPIO_PAR_PCI_GNT3_GNT3		(0xC000)
-#define GPIO_PAR_PCI_GNT3_ATA_DMACK	(0x8000)
-#define GPIO_PAR_PCI_GNT3_GPIO		(0x0000)
-#define GPIO_PAR_PCI_GNT2_GNT2		(0x1000)
-#define GPIO_PAR_PCI_GNT2_GPIO		(0x0000)
-#define GPIO_PAR_PCI_GNT1_GNT1		(0x0400)
-#define GPIO_PAR_PCI_GNT1_GPIO		(0x0000)
-#define GPIO_PAR_PCI_GNT0_GNT0		(0x0100)
-#define GPIO_PAR_PCI_GNT0_GPIO		(0x0000)
-#define GPIO_PAR_PCI_REQ3_UNMASK	(0xFF3F)
-#define GPIO_PAR_PCI_REQ3_REQ3		(0x00C0)
-#define GPIO_PAR_PCI_REQ3_ATA_INTRQ	(0x0080)
-#define GPIO_PAR_PCI_REQ3_GPIO		(0x0000)
-#define GPIO_PAR_PCI_REQ2_REQ2		(0x0010)
-#define GPIO_PAR_PCI_REQ2_GPIO		(0x0000)
-#define GPIO_PAR_PCI_REQ1_REQ1		(0x0040)
-#define GPIO_PAR_PCI_REQ1_GPIO		(0x0000)
-#define GPIO_PAR_PCI_REQ0_REQ0		(0x0001)
-#define GPIO_PAR_PCI_REQ0_GPIO		(0x0000)
-
-/* Bit definitions and macros for MSCR_SDRAM */
-#define GPIO_MSCR_SDRAM_SDCTL(x)	(((x)&0x03))
-#define GPIO_MSCR_SDRAM_SDCLK(x)	(((x)&0x03)<<2)
-#define GPIO_MSCR_SDRAM_SDDQS(x)	(((x)&0x03)<<4)
-#define GPIO_MSCR_SDRAM_SDDATA(x)	(((x)&0x03)<<6)
-#define GPIO_MSCR_SDRAM_SDDATA_UNMASK	(0x3F)
-#define GPIO_MSCR_SDRAM_SDDATA_DDR1	(0xC0)
-#define GPIO_MSCR_SDRAM_SDDATA_DDR2	(0x80)
-#define GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR	(0x40)
-#define GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR	(0x00)
-#define GPIO_MSCR_SDRAM_SDDQS_UNMASK	(0xCF)
-#define GPIO_MSCR_SDRAM_SDDQS_DDR1	(0x30)
-#define GPIO_MSCR_SDRAM_SDDQS_DDR2	(0x20)
-#define GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR	(0x10)
-#define GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR	(0x00)
-#define GPIO_MSCR_SDRAM_SDCLK_UNMASK	(0xF3)
-#define GPIO_MSCR_SDRAM_SDCLK_DDR1	(0x0C)
-#define GPIO_MSCR_SDRAM_SDCLK_DDR2	(0x08)
-#define GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR	(0x04)
-#define GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR	(0x00)
-#define GPIO_MSCR_SDRAM_SDCTL_UNMASK	(0xFC)
-#define GPIO_MSCR_SDRAM_SDCTL_DDR1	(0x03)
-#define GPIO_MSCR_SDRAM_SDCTL_DDR2	(0x02)
-#define GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR	(0x01)
-#define GPIO_MSCR_SDRAM_SDCTL_HS_LPDDR	(0x00)
-
-/* Bit definitions and macros for MSCR_PCI */
-#define GPIO_MSCR_PCI_PCI		(0x01)
-#define GPIO_MSCR_PCI_PCI_HI_66MHZ	(0x01)
-#define GPIO_MSCR_PCI_PCI_LO_33MHZ	(0x00)
-
-/* Bit definitions and macros for DSCR_I2C */
-#define GPIO_DSCR_I2C_I2C(x)		(((x)&0x03))
-#define GPIO_DSCR_I2C_I2C_LOAD_50PF	(0x03)
-#define GPIO_DSCR_I2C_I2C_LOAD_30PF	(0x02)
-#define GPIO_DSCR_I2C_I2C_LOAD_20PF	(0x01)
-#define GPIO_DSCR_I2C_I2C_LOAD_10PF	(0x00)
-
-/* Bit definitions and macros for DSCR_FLEXBUS */
-#define GPIO_DSCR_FLEXBUS_FBADL(x)		(((x)&0x03))
-#define GPIO_DSCR_FLEXBUS_FBADH(x)		(((x)&0x03)<<2)
-#define GPIO_DSCR_FLEXBUS_FBCTL(x)		(((x)&0x03)<<4)
-#define GPIO_DSCR_FLEXBUS_FBCLK(x)		(((x)&0x03)<<6)
-#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_50PF	(0xC0)
-#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_30PF	(0x80)
-#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_20PF	(0x40)
-#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_10PF	(0x00)
-#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_50PF	(0x30)
-#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_30PF	(0x20)
-#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_20PF	(0x10)
-#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_10PF	(0x00)
-#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_50PF	(0x0C)
-#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_30PF	(0x08)
-#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_20PF	(0x04)
-#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_10PF	(0x00)
-#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_50PF	(0x03)
-#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_30PF	(0x02)
-#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_20PF	(0x01)
-#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_10PF	(0x00)
-
-/* Bit definitions and macros for DSCR_FEC */
-#define GPIO_DSCR_FEC_FEC0(x)		(((x)&0x03))
-#define GPIO_DSCR_FEC_FEC1(x)		(((x)&0x03)<<2)
-#define GPIO_DSCR_FEC_FEC1_LOAD_50PF	(0x0C)
-#define GPIO_DSCR_FEC_FEC1_LOAD_30PF	(0x08)
-#define GPIO_DSCR_FEC_FEC1_LOAD_20PF	(0x04)
-#define GPIO_DSCR_FEC_FEC1_LOAD_10PF	(0x00)
-#define GPIO_DSCR_FEC_FEC0_LOAD_50PF	(0x03)
-#define GPIO_DSCR_FEC_FEC0_LOAD_30PF	(0x02)
-#define GPIO_DSCR_FEC_FEC0_LOAD_20PF	(0x01)
-#define GPIO_DSCR_FEC_FEC0_LOAD_10PF	(0x00)
-
-/* Bit definitions and macros for DSCR_UART */
-#define GPIO_DSCR_UART_UART0(x)		(((x)&0x03))
-#define GPIO_DSCR_UART_UART1(x)		(((x)&0x03)<<2)
-#define GPIO_DSCR_UART_UART1_LOAD_50PF	(0x0C)
-#define GPIO_DSCR_UART_UART1_LOAD_30PF	(0x08)
-#define GPIO_DSCR_UART_UART1_LOAD_20PF	(0x04)
-#define GPIO_DSCR_UART_UART1_LOAD_10PF	(0x00)
-#define GPIO_DSCR_UART_UART0_LOAD_50PF	(0x03)
-#define GPIO_DSCR_UART_UART0_LOAD_30PF	(0x02)
-#define GPIO_DSCR_UART_UART0_LOAD_20PF	(0x01)
-#define GPIO_DSCR_UART_UART0_LOAD_10PF	(0x00)
-
-/* Bit definitions and macros for DSCR_DSPI */
-#define GPIO_DSCR_DSPI_DSPI(x)		(((x)&0x03))
-#define GPIO_DSCR_DSPI_DSPI_LOAD_50PF	(0x03)
-#define GPIO_DSCR_DSPI_DSPI_LOAD_30PF	(0x02)
-#define GPIO_DSCR_DSPI_DSPI_LOAD_20PF	(0x01)
-#define GPIO_DSCR_DSPI_DSPI_LOAD_10PF	(0x00)
-
-/* Bit definitions and macros for DSCR_TIMER */
-#define GPIO_DSCR_TIMER_TIMER(x)	(((x)&0x03))
-#define GPIO_DSCR_TIMER_TIMER_LOAD_50PF	(0x03)
-#define GPIO_DSCR_TIMER_TIMER_LOAD_30PF	(0x02)
-#define GPIO_DSCR_TIMER_TIMER_LOAD_20PF	(0x01)
-#define GPIO_DSCR_TIMER_TIMER_LOAD_10PF	(0x00)
-
-/* Bit definitions and macros for DSCR_SSI */
-#define GPIO_DSCR_SSI_SSI(x)		(((x)&0x03))
-#define GPIO_DSCR_SSI_SSI_LOAD_50PF	(0x03)
-#define GPIO_DSCR_SSI_SSI_LOAD_30PF	(0x02)
-#define GPIO_DSCR_SSI_SSI_LOAD_20PF	(0x01)
-#define GPIO_DSCR_SSI_SSI_LOAD_10PF	(0x00)
-
-/* Bit definitions and macros for DSCR_DMA */
-#define GPIO_DSCR_DMA_DMA(x)		(((x)&0x03))
-#define GPIO_DSCR_DMA_DMA_LOAD_50PF	(0x03)
-#define GPIO_DSCR_DMA_DMA_LOAD_30PF	(0x02)
-#define GPIO_DSCR_DMA_DMA_LOAD_20PF	(0x01)
-#define GPIO_DSCR_DMA_DMA_LOAD_10PF	(0x00)
-
-/* Bit definitions and macros for DSCR_DEBUG */
-#define GPIO_DSCR_DEBUG_DEBUG(x)	(((x)&0x03))
-#define GPIO_DSCR_DEBUG_DEBUG_LOAD_50PF	(0x03)
-#define GPIO_DSCR_DEBUG_DEBUG_LOAD_30PF	(0x02)
-#define GPIO_DSCR_DEBUG_DEBUG_LOAD_20PF	(0x01)
-#define GPIO_DSCR_DEBUG_DEBUG_LOAD_10PF	(0x00)
-
-/* Bit definitions and macros for DSCR_RESET */
-#define GPIO_DSCR_RESET_RESET(x)	(((x)&0x03))
-#define GPIO_DSCR_RESET_RESET_LOAD_50PF	(0x03)
-#define GPIO_DSCR_RESET_RESET_LOAD_30PF	(0x02)
-#define GPIO_DSCR_RESET_RESET_LOAD_20PF	(0x01)
-#define GPIO_DSCR_RESET_RESET_LOAD_10PF	(0x00)
-
-/* Bit definitions and macros for DSCR_IRQ */
-#define GPIO_DSCR_IRQ_IRQ(x)		(((x)&0x03))
-#define GPIO_DSCR_IRQ_IRQ_LOAD_50PF	(0x03)
-#define GPIO_DSCR_IRQ_IRQ_LOAD_30PF	(0x02)
-#define GPIO_DSCR_IRQ_IRQ_LOAD_20PF	(0x01)
-#define GPIO_DSCR_IRQ_IRQ_LOAD_10PF	(0x00)
-
-/* Bit definitions and macros for DSCR_USB */
-#define GPIO_DSCR_USB_USB(x)		(((x)&0x03))
-#define GPIO_DSCR_USB_USB_LOAD_50PF	(0x03)
-#define GPIO_DSCR_USB_USB_LOAD_30PF	(0x02)
-#define GPIO_DSCR_USB_USB_LOAD_20PF	(0x01)
-#define GPIO_DSCR_USB_USB_LOAD_10PF	(0x00)
-
-/* Bit definitions and macros for DSCR_ATA */
-#define GPIO_DSCR_ATA_ATA(x)		(((x)&0x03))
-#define GPIO_DSCR_ATA_ATA_LOAD_50PF	(0x03)
-#define GPIO_DSCR_ATA_ATA_LOAD_30PF	(0x02)
-#define GPIO_DSCR_ATA_ATA_LOAD_20PF	(0x01)
-#define GPIO_DSCR_ATA_ATA_LOAD_10PF	(0x00)
-
-/*********************************************************************
-* SDRAM Controller (SDRAMC)
-*********************************************************************/
-
-/* Bit definitions and macros for SDMR */
-#define SDRAMC_SDMR_DDR2_AD(x)		(((x)&0x00003FFF))	/* Address for DDR2 */
-#define SDRAMC_SDMR_CMD			(0x00010000)	/* Command */
-#define SDRAMC_SDMR_AD(x)		(((x)&0x00000FFF)<<18)	/* Address */
-#define SDRAMC_SDMR_BK(x)		(((x)&0x00000003)<<30)	/* Bank Address */
-#define SDRAMC_SDMR_BK_LMR		(0x00000000)
-#define SDRAMC_SDMR_BK_LEMR		(0x40000000)
-
-/* Bit definitions and macros for SDCR */
-#define SDRAMC_SDCR_DPD			(0x00000001)	/* Deep Power-Down Mode */
-#define SDRAMC_SDCR_IPALL		(0x00000002)	/* Initiate Precharge All */
-#define SDRAMC_SDCR_IREF		(0x00000004)	/* Initiate Refresh */
-#define SDRAMC_SDCR_DQS_OE(x)		(((x)&0x00000003)<<10)	/* DQS Output Enable */
-#define SDRAMC_SDCR_MEM_PS		(0x00002000)	/* Data Port Size */
-#define SDRAMC_SDCR_REF_CNT(x)		(((x)&0x0000003F)<<16)	/* Periodic Refresh Counter */
-#define SDRAMC_SDCR_OE_RULE		(0x00400000)	/* Drive Rule Selection */
-#define SDRAMC_SDCR_ADDR_MUX(x)		(((x)&0x00000003)<<24)	/* Internal Address Mux Select */
-#define SDRAMC_SDCR_DDR2_MODE		(0x08000000)	/* DDR2 Mode Select */
-#define SDRAMC_SDCR_REF_EN		(0x10000000)	/* Refresh Enable */
-#define SDRAMC_SDCR_DDR_MODE		(0x20000000)	/* DDR Mode Select */
-#define SDRAMC_SDCR_CKE			(0x40000000)	/* Clock Enable */
-#define SDRAMC_SDCR_MODE_EN		(0x80000000)	/* SDRAM Mode Register Programming Enable */
-#define SDRAMC_SDCR_DQS_OE_BOTH		(0x00000C000)
-
-/* Bit definitions and macros for SDCFG1 */
-#define SDRAMC_SDCFG1_WT_LAT(x)		(((x)&0x00000007)<<4)	/* Write Latency */
-#define SDRAMC_SDCFG1_REF2ACT(x)	(((x)&0x0000000F)<<8)	/* Refresh to active delay */
-#define SDRAMC_SDCFG1_PRE2ACT(x)	(((x)&0x00000007)<<12)	/* Precharge to active delay */
-#define SDRAMC_SDCFG1_ACT2RW(x)		(((x)&0x00000007)<<16)	/* Active to read/write delay */
-#define SDRAMC_SDCFG1_RD_LAT(x)		(((x)&0x0000000F)<<20)	/* Read CAS Latency */
-#define SDRAMC_SDCFG1_SWT2RWP(x)	(((x)&0x00000007)<<24)	/* Single write to read/write/precharge delay */
-#define SDRAMC_SDCFG1_SRD2RWP(x)	(((x)&0x0000000F)<<28)	/* Single read to read/write/precharge delay */
-
-/* Bit definitions and macros for SDCFG2 */
-#define SDRAMC_SDCFG2_BL(x)		(((x)&0x0000000F)<<16)	/* Burst Length */
-#define SDRAMC_SDCFG2_BRD2W(x)		(((x)&0x0000000F)<<20)	/* Burst read to write delay */
-#define SDRAMC_SDCFG2_BWT2RWP(x)	(((x)&0x0000000F)<<24)	/* Burst write to read/write/precharge delay */
-#define SDRAMC_SDCFG2_BRD2RP(x)		(((x)&0x0000000F)<<28)	/* Burst read to read/precharge delay */
-
-/* Bit definitions and macros for SDCS group */
-#define SDRAMC_SDCS_CSSZ(x)		(((x)&0x0000001F))	/* Chip-Select Size */
-#define SDRAMC_SDCS_CSBA(x)		(((x)&0x00000FFF)<<20)	/* Chip-Select Base Address */
-#define SDRAMC_SDCS_BA(x)		((x)&0xFFF00000)
-#define SDRAMC_SDCS_CSSZ_DISABLE	(0x00000000)
-#define SDRAMC_SDCS_CSSZ_1MBYTE		(0x00000013)
-#define SDRAMC_SDCS_CSSZ_2MBYTE		(0x00000014)
-#define SDRAMC_SDCS_CSSZ_4MBYTE		(0x00000015)
-#define SDRAMC_SDCS_CSSZ_8MBYTE		(0x00000016)
-#define SDRAMC_SDCS_CSSZ_16MBYTE	(0x00000017)
-#define SDRAMC_SDCS_CSSZ_32MBYTE	(0x00000018)
-#define SDRAMC_SDCS_CSSZ_64MBYTE	(0x00000019)
-#define SDRAMC_SDCS_CSSZ_128MBYTE	(0x0000001A)
-#define SDRAMC_SDCS_CSSZ_256MBYTE	(0x0000001B)
-#define SDRAMC_SDCS_CSSZ_512MBYTE	(0x0000001C)
-#define SDRAMC_SDCS_CSSZ_1GBYTE		(0x0000001D)
-#define SDRAMC_SDCS_CSSZ_2GBYTE		(0x0000001E)
-#define SDRAMC_SDCS_CSSZ_4GBYTE		(0x0000001F)
-
-/*********************************************************************
-* Phase Locked Loop (PLL)
-*********************************************************************/
-
-/* Bit definitions and macros for PCR */
-#define PLL_PCR_OUTDIV1(x)		(((x)&0x0000000F))	/* Output divider for CPU clock frequency */
-#define PLL_PCR_OUTDIV2(x)		(((x)&0x0000000F)<<4)	/* Output divider for internal bus clock frequency */
-#define PLL_PCR_OUTDIV3(x)		(((x)&0x0000000F)<<8)	/* Output divider for Flexbus clock frequency */
-#define PLL_PCR_OUTDIV4(x)		(((x)&0x0000000F)<<12)	/* Output divider for PCI clock frequency */
-#define PLL_PCR_OUTDIV5(x)		(((x)&0x0000000F)<<16)	/* Output divider for USB clock frequency */
-#define PLL_PCR_PFDR(x)			(((x)&0x000000FF)<<24)	/* Feedback divider for VCO frequency */
-#define PLL_PCR_PFDR_MASK		(0x000F0000)
-#define PLL_PCR_OUTDIV5_MASK		(0x000F0000)
-#define PLL_PCR_OUTDIV4_MASK		(0x0000F000)
-#define PLL_PCR_OUTDIV3_MASK		(0x00000F00)
-#define PLL_PCR_OUTDIV2_MASK		(0x000000F0)
-#define PLL_PCR_OUTDIV1_MASK		(0x0000000F)
-
-/* Bit definitions and macros for PSR */
-#define PLL_PSR_LOCKS			(0x00000001)	/* PLL lost lock - sticky */
-#define PLL_PSR_LOCK			(0x00000002)	/* PLL lock status */
-#define PLL_PSR_LOLIRQ			(0x00000004)	/* PLL loss-of-lock interrupt enable */
-#define PLL_PSR_LOLRE			(0x00000008)	/* PLL loss-of-lock reset enable */
-
-/*********************************************************************
-* PCI
-*********************************************************************/
-
-/* Bit definitions and macros for SCR */
-#define PCI_SCR_PE			(0x80000000)	/* Parity Error detected */
-#define PCI_SCR_SE			(0x40000000)	/* System error signalled */
-#define PCI_SCR_MA			(0x20000000)	/* Master aboart received */
-#define PCI_SCR_TR			(0x10000000)	/* Target abort received */
-#define PCI_SCR_TS			(0x08000000)	/* Target abort signalled */
-#define PCI_SCR_DT			(0x06000000)	/* PCI_DEVSEL timing */
-#define PCI_SCR_DP			(0x01000000)	/* Master data parity err */
-#define PCI_SCR_FC			(0x00800000)	/* Fast back-to-back */
-#define PCI_SCR_R			(0x00400000)	/* Reserved */
-#define PCI_SCR_66M			(0x00200000)	/* 66Mhz */
-#define PCI_SCR_C			(0x00100000)	/* Capabilities list */
-#define PCI_SCR_F			(0x00000200)	/* Fast back-to-back enable */
-#define PCI_SCR_S			(0x00000100)	/* SERR enable */
-#define PCI_SCR_ST			(0x00000080)	/* Addr and Data stepping */
-#define PCI_SCR_PER			(0x00000040)	/* Parity error response */
-#define PCI_SCR_V			(0x00000020)	/* VGA palette snoop enable */
-#define PCI_SCR_MW			(0x00000010)	/* Memory write and invalidate enable */
-#define PCI_SCR_SP			(0x00000008)	/* Special cycle monitor or ignore */
-#define PCI_SCR_B			(0x00000004)	/* Bus master enable */
-#define PCI_SCR_M			(0x00000002)	/* Memory access control */
-#define PCI_SCR_IO			(0x00000001)	/* I/O access control */
-
-#define PCI_CR1_BIST(x)			((x & 0xFF) << 24)	/* Built in self test */
-#define PCI_CR1_HDR(x)			((x & 0xFF) << 16)	/* Header type */
-#define PCI_CR1_LTMR(x)			((x & 0xF8) << 8)	/* Latency timer */
-#define PCI_CR1_CLS(x)			(x & 0x0F)	/* Cache line size */
-
-#define PCI_BAR_BAR0(x)			(x & 0xFFFC0000)
-#define PCI_BAR_BAR1(x)			(x & 0xFFF00000)
-#define PCI_BAR_BAR2(x)			(x & 0xFFC00000)
-#define PCI_BAR_BAR3(x)			(x & 0xFF000000)
-#define PCI_BAR_BAR4(x)			(x & 0xF8000000)
-#define PCI_BAR_BAR5(x)			(x & 0xE0000000)
-#define PCI_BAR_PREF			(0x00000004)	/* Prefetchable access */
-#define PCI_BAR_RANGE			(0x00000002)	/* Fixed to 00 */
-#define PCI_BAR_IO_M			(0x00000001)	/* IO / memory space */
-
-#define PCI_CR2_MAXLAT(x)		((x & 0xFF) << 24)	/* Maximum latency */
-#define PCI_CR2_MINGNT(x)		((x & 0xFF) << 16)	/* Minimum grant */
-#define PCI_CR2_INTPIN(x)		((x & 0xFF) << 8)	/* Interrupt Pin */
-#define PCI_CR2_INTLIN(x)		(x & 0xFF)	/* Interrupt Line */
-
-#define PCI_GSCR_DRD			(0x80000000)	/* Delayed read discarded */
-#define PCI_GSCR_PE			(0x20000000)	/* PCI_PERR detected */
-#define PCI_GSCR_SE			(0x10000000)	/* SERR detected */
-#define PCI_GSCR_ER			(0x08000000)	/* Error response detected */
-#define PCI_GSCR_DRDE			(0x00008000)	/* Delayed read discarded enable */
-#define PCI_GSCR_PEE			(0x00002000)	/* PERR detected interrupt enable */
-#define PCI_GSCR_SEE			(0x00001000)	/* SERR detected interrupt enable */
-#define PCI_GSCR_PR			(0x00000001)	/* PCI reset */
-
-#define PCI_TCR1_LD			(0x01000000)	/* Latency rule disable */
-#define PCI_TCR1_PID			(0x00020000)	/* Prefetch invalidate and disable */
-#define PCI_TCR1_P			(0x00010000)	/* Prefetch reads */
-#define PCI_TCR1_WCD			(0x00000100)	/* Write combine disable */
-
-#define PCI_TCR2_B5E			(0x00002000)	/*  */
-#define PCI_TCR2_B4E			(0x00001000)	/*  */
-#define PCI_TCR2_B3E			(0x00000800)	/*  */
-#define PCI_TCR2_B2E			(0x00000400)	/*  */
-#define PCI_TCR2_B1E			(0x00000200)	/*  */
-#define PCI_TCR2_B0E			(0x00000100)	/*  */
-#define PCI_TCR2_CR			(0x00000001)	/*  */
-
-#define PCI_TBATR_BAT(x)		((x & 0xFFF) << 20)
-#define PCI_TBATR_EN			(0x00000001)	/* Enable */
-
-#define PCI_IWCR_W0C_IO			(0x08000000)	/* Windows Maps to PCI I/O */
-#define PCI_IWCR_W0C_PRC_RDMUL		(0x04000000)	/* PCI Memory Read multiple */
-#define PCI_IWCR_W0C_PRC_RDLN		(0x02000000)	/* PCI Memory Read line */
-#define PCI_IWCR_W0C_PRC_RD		(0x00000000)	/* PCI Memory Read */
-#define PCI_IWCR_W0C_EN			(0x01000000)	/* Enable - Register initialize */
-#define PCI_IWCR_W1C_IO			(0x00080000)	/* Windows Maps to PCI I/O */
-#define PCI_IWCR_W1C_PRC_RDMUL		(0x00040000)	/* PCI Memory Read multiple */
-#define PCI_IWCR_W1C_PRC_RDLN		(0x00020000)	/* PCI Memory Read line */
-#define PCI_IWCR_W1C_PRC_RD		(0x00000000)	/* PCI Memory Read */
-#define PCI_IWCR_W1C_EN			(0x00010000)	/* Enable - Register initialize */
-#define PCI_IWCR_W2C_IO			(0x00000800)	/* Windows Maps to PCI I/O */
-#define PCI_IWCR_W2C_PRC_RDMUL		(0x00000400)	/* PCI Memory Read multiple */
-#define PCI_IWCR_W2C_PRC_RDLN		(0x00000200)	/* PCI Memory Read line */
-#define PCI_IWCR_W2C_PRC_RD		(0x00000000)	/* PCI Memory Read */
-#define PCI_IWCR_W2C_EN			(0x00000100)	/* Enable - Register initialize */
-
-#define PCI_ICR_REE			(0x04000000)	/* Retry error enable */
-#define PCI_ICR_IAE			(0x02000000)	/* Initiator abort enable */
-#define PCI_ICR_TAE			(0x01000000)	/* Target abort enable */
-#define PCI_ICR_MAXRETRY(x)		((x) & 0x000000FF)
-
-/********************************************************************/
-
-#endif				/* __MCF5445X__ */
diff --git a/board/freescale/m54451evb/Kconfig b/board/freescale/m54451evb/Kconfig
deleted file mode 100644
index f460e51c9b..0000000000
--- a/board/freescale/m54451evb/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_M54451EVB
-
-config SYS_CPU
-	default "mcf5445x"
-
-config SYS_BOARD
-	default "m54451evb"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "M54451EVB"
-
-endif
diff --git a/board/freescale/m54451evb/MAINTAINERS b/board/freescale/m54451evb/MAINTAINERS
deleted file mode 100644
index 52a2681080..0000000000
--- a/board/freescale/m54451evb/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-M54451EVB BOARD
-#M:	-
-S:	Maintained
-F:	board/freescale/m54451evb/
-F:	include/configs/M54451EVB.h
-F:	configs/M54451EVB_defconfig
-F:	configs/M54451EVB_stmicro_defconfig
diff --git a/board/freescale/m54451evb/Makefile b/board/freescale/m54451evb/Makefile
deleted file mode 100644
index 8c2c6a9eb7..0000000000
--- a/board/freescale/m54451evb/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y	= m54451evb.o
-extra-y	+= sbf_dram_init.o
diff --git a/board/freescale/m54451evb/m54451evb.c b/board/freescale/m54451evb/m54451evb.c
deleted file mode 100644
index a4ddc69166..0000000000
--- a/board/freescale/m54451evb/m54451evb.c
+++ /dev/null
@@ -1,98 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-#include <common.h>
-#include <init.h>
-#include <spi.h>
-#include <asm/global_data.h>
-#include <asm/immap.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	/*
-	 * need to to:
-	 * Check serial flash size. if 2mb evb, else 8mb demo
-	 */
-	puts("Board: ");
-	puts("Freescale M54451 EVB\n");
-	return 0;
-};
-
-int dram_init(void)
-{
-	u32 dramsize;
-#ifdef CONFIG_CF_SBF
-	/*
-	 * Serial Boot: The dram is already initialized in start.S
-	 * only require to return DRAM size
-	 */
-	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
-#else
-	sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
-	gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
-	u32 i;
-
-	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
-
-	if ((in_be32(&sdram->sdcfg1) == CONFIG_SYS_SDRAM_CFG1) &&
-	    (in_be32(&sdram->sdcfg2) == CONFIG_SYS_SDRAM_CFG2))
-		return dramsize;
-
-	for (i = 0x13; i < 0x20; i++) {
-		if (dramsize == (1 << i))
-			break;
-	}
-	i--;
-
-	out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
-
-	out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
-
-	out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
-	out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
-
-	udelay(200);
-
-	/* Issue PALL */
-	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
-	__asm__("nop");
-
-	/* Perform two refresh cycles */
-	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
-	__asm__("nop");
-	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
-	__asm__("nop");
-
-	/* Issue LEMR */
-	out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
-	__asm__("nop");
-	out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
-	__asm__("nop");
-
-	out_be32(&sdram->sdcr,
-		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000);
-
-	udelay(100);
-#endif
-	gd->ram_size = dramsize;
-
-	return 0;
-};
-
-int testdram(void)
-{
-	/* TODO: XXX XXX XXX */
-	printf("DRAM test not implemented!\n");
-
-	return (0);
-}
diff --git a/board/freescale/m54451evb/sbf_dram_init.S b/board/freescale/m54451evb/sbf_dram_init.S
deleted file mode 100644
index ee08cd1ecb..0000000000
--- a/board/freescale/m54451evb/sbf_dram_init.S
+++ /dev/null
@@ -1,96 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Board-specific sbf ddr/sdram init.
- *
- * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
- */
-
- #include <config.h>
-
-.global sbf_dram_init
-.text
-
-sbf_dram_init:
-	/* Dram Initialization a1, a2, and d0 */
-	/* mscr sdram */
-	move.l	#0xFC0A4074, %a1
-	move.b	#(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
-	nop
-
-	/* SDRAM Chip 0 and 1 */
-	move.l	#0xFC0B8110, %a1
-	move.l	#0xFC0B8114, %a2
-
-	/* calculate the size */
-	move.l	#0x13, %d1
-	move.l	#(CONFIG_SYS_SDRAM_SIZE), %d2
-#ifdef CONFIG_SYS_SDRAM_BASE1
-	lsr.l	#1, %d2
-#endif
-
-dramsz_loop:
-	lsr.l	#1, %d2
-	add.l	#1, %d1
-	cmp.l	#1, %d2
-	bne	dramsz_loop
-#ifdef CONFIG_SYS_NAND_BOOT
-	beq	asm_nand_chk_status
-#endif
-	/* SDRAM Chip 0 and 1 */
-	move.l	#(CONFIG_SYS_SDRAM_BASE), (%a1)
-	or.l	%d1, (%a1)
-#ifdef CONFIG_SYS_SDRAM_BASE1
-	move.l	#(CONFIG_SYS_SDRAM_BASE1), (%a2)
-	or.l	%d1, (%a2)
-#endif
-	nop
-
-	/* dram cfg1 and cfg2 */
-	move.l	#0xFC0B8008, %a1
-	move.l	#(CONFIG_SYS_SDRAM_CFG1), (%a1)
-	nop
-	move.l	#0xFC0B800C, %a2
-	move.l	#(CONFIG_SYS_SDRAM_CFG2), (%a2)
-	nop
-
-	move.l	#0xFC0B8000, %a1	/* Mode */
-	move.l	#0xFC0B8004, %a2	/* Ctrl */
-
-	/* Issue PALL */
-	move.l	#(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
-	nop
-
-	move.l	#1000, %d1
-	bsr	asm_delay
-
-	/* Issue PALL */
-	move.l	#(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
-	nop
-
-	/* Perform two refresh cycles */
-	move.l	#(CONFIG_SYS_SDRAM_CTRL + 4), %d0
-	nop
-	move.l	%d0, (%a2)
-	move.l	%d0, (%a2)
-	nop
-
-	/* Issue LEMR */
-	move.l	#(CONFIG_SYS_SDRAM_MODE), (%a1)
-	nop
-	move.l	#(CONFIG_SYS_SDRAM_EMOD), (%a1)
-
-	move.l	#500, %d1
-	bsr	asm_delay
-
-	move.l	#(CONFIG_SYS_SDRAM_CTRL), %d1
-	and.l	#0x7FFFFFFF, %d1
-
-	or.l	#0x10000C00, %d1
-
-	move.l	%d1, (%a2)
-	nop
-
-	move.l	#2000, %d1
-	bsr	asm_delay
-
-	rts
diff --git a/configs/M54451EVB_defconfig b/configs/M54451EVB_defconfig
deleted file mode 100644
index a3583e5c5b..0000000000
--- a/configs/M54451EVB_defconfig
+++ /dev/null
@@ -1,40 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0x0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="M54451EVB"
-CONFIG_TARGET_M54451EVB=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_INPUT_CLKSRC=24000000"
-CONFIG_BOOTDELAY=1
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)"
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x40000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_DM_ETH=y
-CONFIG_MCFFEC=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CF_SPI=y
diff --git a/configs/M54451EVB_stmicro_defconfig b/configs/M54451EVB_stmicro_defconfig
deleted file mode 100644
index 5f5e6a55f6..0000000000
--- a/configs/M54451EVB_stmicro_defconfig
+++ /dev/null
@@ -1,42 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0x47E00000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x20000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DEFAULT_DEVICE_TREE="M54451EVB_stmicro"
-CONFIG_TARGET_M54451EVB=y
-CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT,SYS_INPUT_CLKSRC=24000000"
-CONFIG_BOOTDELAY=1
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)"
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_CS=y
-CONFIG_ENV_SPI_CS=1
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_DM_ETH=y
-CONFIG_MCFFEC=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CF_SPI=y
diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c
index 43bb761483..cef9eecac2 100644
--- a/drivers/net/mcffec.c
+++ b/drivers/net/mcffec.c
@@ -105,17 +105,11 @@ static void set_fec_duplex_speed(volatile fec_t *fecp, int dup_spd)
 	}
 
 	if ((dup_spd & 0xFFFF) == _100BASET) {
-#ifdef CONFIG_MCF5445x
-		fecp->rcr &= ~0x200;	/* disabled 10T base */
-#endif
 #ifdef MII_DEBUG
 		printf("100Mbps\n");
 #endif
 		bd->bi_ethspeed = 100;
 	} else {
-#ifdef CONFIG_MCF5445x
-		fecp->rcr |= 0x200;	/* enabled 10T base */
-#endif
 #ifdef MII_DEBUG
 		printf("10Mbps\n");
 #endif
diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h
deleted file mode 100644
index f5bafb70e7..0000000000
--- a/include/configs/M54451EVB.h
+++ /dev/null
@@ -1,242 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Freescale MCF54451 EVB board.
- *
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef _M54451EVB_H
-#define _M54451EVB_H
-
-#include <linux/stringify.h>
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_M54451EVB	/* M54451EVB board */
-
-#define CONFIG_MCFUART
-#define CONFIG_SYS_UART_PORT		(0)
-
-#define LDS_BOARD_TEXT                  board/freescale/m54451evb/sbf_dram_init.o (.text*)
-
-#undef CONFIG_WATCHDOG
-
-#define CONFIG_TIMESTAMP	/* Print image info with timestamp */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/* Network configuration */
-#ifdef CONFIG_MCFFEC
-#	define CONFIG_MII_INIT		1
-#	define CONFIG_SYS_DISCOVER_PHY
-#	define CONFIG_SYS_RX_ETH_BUFFER	8
-#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-#	define CONFIG_ETHPRIME		"FEC0"
-#	define CONFIG_IPADDR		192.162.1.2
-#	define CONFIG_NETMASK		255.255.255.0
-#	define CONFIG_SERVERIP		192.162.1.1
-#	define CONFIG_GATEWAYIP		192.162.1.1
-
-/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
-#	ifndef CONFIG_SYS_DISCOVER_PHY
-#		define FECDUPLEX	FULL
-#		define FECSPEED		_100BASET
-#	else
-#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-#		endif
-#	endif			/* CONFIG_SYS_DISCOVER_PHY */
-#endif
-
-#define CONFIG_HOSTNAME		"M54451EVB"
-#ifdef CONFIG_SYS_STMICRO_BOOT
-/* ST Micro serial flash */
-#define	CONFIG_SYS_LOAD_ADDR2		0x40010007
-#define CONFIG_EXTRA_ENV_SETTINGS		\
-	"netdev=eth0\0"				\
-	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
-	"loadaddr=0x40010000\0"			\
-	"sbfhdr=sbfhdr.bin\0"			\
-	"uboot=u-boot.bin\0"			\
-	"load=tftp ${loadaddr} ${sbfhdr};"	\
-	"tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"	\
-	"upd=run load; run prog\0"		\
-	"prog=sf probe 0:1 1000000 3;"		\
-	"sf erase 0 30000;"			\
-	"sf write ${loadaddr} 0 30000;"		\
-	"save\0"				\
-	""
-#else
-#define CONFIG_SYS_UBOOT_END	0x3FFFF
-#define CONFIG_EXTRA_ENV_SETTINGS		\
-	"netdev=eth0\0"				\
-	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
-	"loadaddr=40010000\0"			\
-	"u-boot=u-boot.bin\0"			\
-	"load=tftp ${loadaddr) ${u-boot}\0"	\
-	"upd=run load; run prog\0"		\
-	"prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END)	\
-	"; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;"	\
-	"cp.b ${loadaddr} 0 ${filesize};"	\
-	"save\0"				\
-	""
-#endif
-
-/* Realtime clock */
-#define CONFIG_MCFRTC
-#undef RTC_DEBUG
-#define CONFIG_SYS_RTC_OSCILLATOR	(32 * CONFIG_SYS_HZ)
-
-/* Timer */
-#define CONFIG_MCFTMR
-
-/* I2c */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	80000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
-#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR
-
-/* DSPI and Serial Flash */
-#define CONFIG_CF_DSPI
-#define CONFIG_SERIAL_FLASH
-#define CONFIG_SYS_SBFHDR_SIZE		0x7
-
-/* Input, PCI, Flexbus, and VCO */
-#define CONFIG_EXTRA_CLOCK
-
-#define CONFIG_PRAM			2048	/* 2048 KB */
-
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
-
-#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x10000)
-
-#define CONFIG_SYS_MBAR			0xFC000000
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* Size of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL	0x221
-#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
-#define CONFIG_SYS_SDRAM_SIZE		128	/* SDRAM size in MB */
-#define CONFIG_SYS_SDRAM_CFG1		0x33633F30
-#define CONFIG_SYS_SDRAM_CFG2		0x57670000
-#define CONFIG_SYS_SDRAM_CTRL		0xE20D2C00
-#define CONFIG_SYS_SDRAM_EMOD		0x80810000
-#define CONFIG_SYS_SDRAM_MODE		0x008D0000
-#define CONFIG_SYS_SDRAM_DRV_STRENGTH	0x44
-
-#ifdef CONFIG_CF_SBF
-#	define CONFIG_SERIAL_BOOT
-#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_TEXT_BASE + 0x400)
-#else
-#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
-#endif
-#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-
-/* Reserve 256 kB for malloc() */
-#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization ??
- */
-/* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
-
-/* Configuration for environment
- * Environment is not embedded in u-boot. First time runing may have env
- * crc error warning if there is no correct environment on the flash.
- */
-
-/* FLASH organization */
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
-
-#ifdef CONFIG_SYS_FLASH_CFI
-
-#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
-#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
-#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
-#	define CONFIG_SYS_FLASH_CHECKSUM
-#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE }
-
-#endif
-
-/*
- * This is setting for JFFS2 support in u-boot.
- * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
- */
-#ifdef CONFIG_CMD_JFFS2
-#	define CONFIG_JFFS2_DEV		"nor0"
-#	define CONFIG_JFFS2_PART_SIZE	0x01000000
-#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH0_BASE + 0x500000)
-#endif
-
-/* Cache Configuration */
-#define CONFIG_SYS_CACHELINE_SIZE		16
-
-#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA)
-#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
-#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
-					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
-					 CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_IEC | \
-					 CF_CACR_ICINVA | CF_CACR_EUSP)
-#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
-					 CF_CACR_DEC | CF_CACR_DDCM_P | \
-					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
-
-/*-----------------------------------------------------------------------
- * Memory bank definitions
- */
-/*
- * CS0 - NOR Flash 16MB
- * CS1 - Available
- * CS2 - Available
- * CS3 - Available
- * CS4 - Available
- * CS5 - Available
- */
-
- /* Flash */
-#define CONFIG_SYS_CS0_BASE		0x00000000
-#define CONFIG_SYS_CS0_MASK		0x00FF0001
-#define CONFIG_SYS_CS0_CTRL		0x00004D80
-
-#define CONFIG_SYS_SPANSION_BASE	CONFIG_SYS_CS0_BASE
-
-#endif				/* _M54451EVB_H */