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authorJim Liu <jim.t90615@gmail.com>2023-05-09 10:07:34 +0300
committerTom Rini <trini@konsulko.com>2023-06-01 19:32:03 +0300
commitf517f61ba85e33dc283c7f714babcb146b7e7dc4 (patch)
tree04bdfa0a47fa8b863b278449c0e490451a8bf90e
parent703da6d7076134c34a6d2a1805bac1ecdc5e1792 (diff)
downloadu-boot-f517f61ba85e33dc283c7f714babcb146b7e7dc4.tar.xz
pinctrl: nuvoton: set output state before enabling the output
The default output state may be different to request, change the configuration sequence to avoid glitch. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
-rw-r--r--drivers/gpio/npcm_gpio.c6
-rw-r--r--drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c4
-rw-r--r--drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c4
3 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpio/npcm_gpio.c b/drivers/gpio/npcm_gpio.c
index 8afd57fa8e..98e5dc79c1 100644
--- a/drivers/gpio/npcm_gpio.c
+++ b/drivers/gpio/npcm_gpio.c
@@ -37,14 +37,14 @@ static int npcm_gpio_direction_output(struct udevice *dev, unsigned int offset,
{
struct npcm_gpio_priv *priv = dev_get_priv(dev);
- clrbits_le32(priv->base + GPIO_IEM, BIT(offset));
- writel(BIT(offset), priv->base + GPIO_OES);
-
if (value)
setbits_le32(priv->base + GPIO_DOUT, BIT(offset));
else
clrbits_le32(priv->base + GPIO_DOUT, BIT(offset));
+ clrbits_le32(priv->base + GPIO_IEM, BIT(offset));
+ writel(BIT(offset), priv->base + GPIO_OES);
+
return 0;
}
diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
index 1ad8bfbd88..92513822e7 100644
--- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
@@ -1552,12 +1552,12 @@ static int npcm7xx_pinconf_set(struct udevice *dev, unsigned int pin,
setbits_le32(base + NPCM7XX_GP_N_OES, BIT(gpio));
case PIN_CONFIG_OUTPUT:
dev_dbg(dev, "set pin %d output %d\n", pin, arg);
- clrbits_le32(base + NPCM7XX_GP_N_IEM, BIT(gpio));
- setbits_le32(base + NPCM7XX_GP_N_OES, BIT(gpio));
if (arg)
setbits_le32(base + NPCM7XX_GP_N_DOUT, BIT(gpio));
else
clrbits_le32(base + NPCM7XX_GP_N_DOUT, BIT(gpio));
+ clrbits_le32(base + NPCM7XX_GP_N_IEM, BIT(gpio));
+ setbits_le32(base + NPCM7XX_GP_N_OES, BIT(gpio));
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
dev_dbg(dev, "set pin %d push pull\n", pin);
diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
index 0ec47e9577..f18be08518 100644
--- a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
@@ -900,12 +900,12 @@ static int npcm8xx_pinconf_set(struct udevice *dev, unsigned int selector,
setbits_le32(base + GPIO_OES, BIT(gpio));
case PIN_CONFIG_OUTPUT:
dev_dbg(dev, "set pin %d output %d\n", pin, arg);
- clrbits_le32(base + GPIO_IEM, BIT(gpio));
- setbits_le32(base + GPIO_OES, BIT(gpio));
if (arg)
setbits_le32(base + GPIO_DOUT, BIT(gpio));
else
clrbits_le32(base + GPIO_DOUT, BIT(gpio));
+ clrbits_le32(base + GPIO_IEM, BIT(gpio));
+ setbits_le32(base + GPIO_OES, BIT(gpio));
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
dev_dbg(dev, "set pin %d push pull\n", pin);