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authorSimon Glass <sjg@chromium.org>2020-12-19 20:39:58 +0300
committerSimon Glass <sjg@chromium.org>2021-01-05 22:24:41 +0300
commitf6257f7914858cd99219feb3185c679137857b60 (patch)
tree7fc87dd2f5c8d0411434911a04bf4ff75c5b8c66
parent366c4eb4b5df420de3cc32be3089bef68a883d97 (diff)
downloadu-boot-f6257f7914858cd99219feb3185c679137857b60.tar.xz
x86: Move priv/plat structs for intel_common to headers
With the new of-platdata, these need to be available to dt_platdata.c so must be in header files. Move them. Signed-off-by: Simon Glass <sjg@chromium.org>
-rw-r--r--arch/x86/cpu/intel_common/itss.c19
-rw-r--r--arch/x86/cpu/intel_common/p2sb.c9
-rw-r--r--arch/x86/include/asm/itss.h21
-rw-r--r--arch/x86/include/asm/p2sb.h18
4 files changed, 40 insertions, 27 deletions
diff --git a/arch/x86/cpu/intel_common/itss.c b/arch/x86/cpu/intel_common/itss.c
index 6515d1f471..ae4de4ca8c 100644
--- a/arch/x86/cpu/intel_common/itss.c
+++ b/arch/x86/cpu/intel_common/itss.c
@@ -19,25 +19,6 @@
#include <spl.h>
#include <asm/itss.h>
-struct itss_plat {
-#if CONFIG_IS_ENABLED(OF_PLATDATA)
- /* Put this first since driver model will copy the data here */
- struct dtd_intel_itss dtplat;
-#endif
-};
-
-/* struct pmc_route - Routing for PMC to GPIO */
-struct pmc_route {
- u32 pmc;
- u32 gpio;
-};
-
-struct itss_priv {
- struct pmc_route *route;
- uint route_count;
- u32 irq_snapshot[NUM_IPC_REGS];
-};
-
static int set_polarity(struct udevice *dev, uint irq, bool active_low)
{
u32 mask;
diff --git a/arch/x86/cpu/intel_common/p2sb.c b/arch/x86/cpu/intel_common/p2sb.c
index cb901f265e..d73ae438bb 100644
--- a/arch/x86/cpu/intel_common/p2sb.c
+++ b/arch/x86/cpu/intel_common/p2sb.c
@@ -13,20 +13,13 @@
#include <log.h>
#include <p2sb.h>
#include <spl.h>
+#include <asm/p2sb.h>
#include <asm/pci.h>
#include <linux/bitops.h>
#define PCH_P2SB_E0 0xe0
#define HIDE_BIT BIT(0)
-struct p2sb_plat {
-#if CONFIG_IS_ENABLED(OF_PLATDATA)
- struct dtd_intel_p2sb dtplat;
-#endif
- ulong mmio_base;
- pci_dev_t bdf;
-};
-
/* PCI config space registers */
#define HPTC_OFFSET 0x60
#define HPTC_ADDR_ENABLE_BIT BIT(7)
diff --git a/arch/x86/include/asm/itss.h b/arch/x86/include/asm/itss.h
index f7d3240384..6d4793277e 100644
--- a/arch/x86/include/asm/itss.h
+++ b/arch/x86/include/asm/itss.h
@@ -11,6 +11,8 @@
#ifndef _ASM_ARCH_ITSS_H
#define _ASM_ARCH_ITSS_H
+#include <irq.h>
+
#define GPIO_IRQ_START 50
#define GPIO_IRQ_END ITSS_MAX_IRQ
@@ -42,4 +44,23 @@
/* ITSS Power reduction control */
#define PCR_ITSS_ITSSPRC 0x3300
+struct itss_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ /* Put this first since driver model will copy the data here */
+ struct dtd_intel_itss dtplat;
+#endif
+};
+
+/* struct pmc_route - Routing for PMC to GPIO */
+struct pmc_route {
+ u32 pmc;
+ u32 gpio;
+};
+
+struct itss_priv {
+ struct pmc_route *route;
+ uint route_count;
+ u32 irq_snapshot[NUM_IPC_REGS];
+};
+
#endif /* _ASM_ARCH_ITSS_H */
diff --git a/arch/x86/include/asm/p2sb.h b/arch/x86/include/asm/p2sb.h
new file mode 100644
index 0000000000..6f63eae8e2
--- /dev/null
+++ b/arch/x86/include/asm/p2sb.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Google LLC
+ */
+
+#ifndef ASM_P2SB_H
+#define ASM_P2SB_H
+
+/* Platform data for the P2SB */
+struct p2sb_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct dtd_intel_p2sb dtplat;
+#endif
+ ulong mmio_base;
+ pci_dev_t bdf;
+};
+
+#endif /* ASM_P2SB_H */