diff options
author | Vasily Khoruzhick <anarsoul@gmail.com> | 2016-03-21 04:37:07 +0300 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2016-03-27 16:13:00 +0300 |
commit | 9cfc05985319c52933d84a7609fc8b143b1ff18a (patch) | |
tree | c69d20955f63785f9da083a0253b073141723001 /arch/arm/cpu/pxa | |
parent | 9ddde3e6ce8abd97d397e3915204a6981d287e42 (diff) | |
download | u-boot-9cfc05985319c52933d84a7609fc8b143b1ff18a.tar.xz |
pxa: add support for D- and I- caches
Tested with OHCI and pxafb drivers - no issues found
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Diffstat (limited to 'arch/arm/cpu/pxa')
-rw-r--r-- | arch/arm/cpu/pxa/Makefile | 1 | ||||
-rw-r--r-- | arch/arm/cpu/pxa/cache.c | 62 | ||||
-rw-r--r-- | arch/arm/cpu/pxa/pxa2xx.c | 10 |
3 files changed, 73 insertions, 0 deletions
diff --git a/arch/arm/cpu/pxa/Makefile b/arch/arm/cpu/pxa/Makefile index 3ee08cd188..79fcb7398b 100644 --- a/arch/arm/cpu/pxa/Makefile +++ b/arch/arm/cpu/pxa/Makefile @@ -14,3 +14,4 @@ obj-y += cpuinfo.o obj-y += timer.o obj-y += usb.o obj-y += relocate.o +obj-y += cache.o diff --git a/arch/arm/cpu/pxa/cache.c b/arch/arm/cpu/pxa/cache.c new file mode 100644 index 0000000000..7aba112c71 --- /dev/null +++ b/arch/arm/cpu/pxa/cache.c @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2016 Vasily Khoruzhick <anarsoul@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/types.h> +#include <common.h> + +#ifndef CONFIG_SYS_DCACHE_OFF + +#ifndef CONFIG_SYS_CACHELINE_SIZE +#define CONFIG_SYS_CACHELINE_SIZE 32 +#endif + +void invalidate_dcache_all(void) +{ + /* Flush/Invalidate I cache */ + asm volatile("mcr p15, 0, %0, c7, c5, 0\n" : : "r"(0)); + /* Flush/Invalidate D cache */ + asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0)); +} + +void flush_dcache_all(void) +{ + return invalidate_dcache_all(); +} + +void invalidate_dcache_range(unsigned long start, unsigned long stop) +{ + start &= ~(CONFIG_SYS_CACHELINE_SIZE - 1); + stop &= ~(CONFIG_SYS_CACHELINE_SIZE - 1); + + while (start <= stop) { + asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start)); + start += CONFIG_SYS_CACHELINE_SIZE; + } +} + +void flush_dcache_range(unsigned long start, unsigned long stop) +{ + return invalidate_dcache_range(start, stop); +} +#else /* #ifndef CONFIG_SYS_DCACHE_OFF */ +void invalidate_dcache_all(void) +{ +} + +void flush_dcache_all(void) +{ +} +#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ + +/* + * Stub implementations for l2 cache operations + */ + +__weak void l2_cache_disable(void) {} + +#if defined CONFIG_SYS_THUMB_BUILD +__weak void invalidate_l2_cache(void) {} +#endif diff --git a/arch/arm/cpu/pxa/pxa2xx.c b/arch/arm/cpu/pxa/pxa2xx.c index 2f12fb9c82..77f0ef2de4 100644 --- a/arch/arm/cpu/pxa/pxa2xx.c +++ b/arch/arm/cpu/pxa/pxa2xx.c @@ -284,3 +284,13 @@ void reset_cpu(ulong ignored) for (;;) ; } + +void enable_caches(void) +{ +#ifndef CONFIG_SYS_ICACHE_OFF + icache_enable(); +#endif +#ifndef CONFIG_SYS_DCACHE_OFF + dcache_enable(); +#endif +} |