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| author | Icenowy Zheng <icenowy@aosc.xyz> | 2017-06-03 12:10:20 +0300 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2017-06-08 20:07:55 +0300 |
| commit | 67337e68a5a88ecbe4ae0df6a91c653f2817c3e1 (patch) | |
| tree | 8be8c29aed216748488cdbbea7f578cd77a148a2 /arch/arm/mach-sunxi/dram_sunxi_dw.c | |
| parent | 176868bc65c15f10e585209af69bca93a0d18a69 (diff) | |
| download | u-boot-67337e68a5a88ecbe4ae0df6a91c653f2817c3e1.tar.xz | |
sunxi: add support for the DDR2 in V3s SoC
Allwinner V3s SoC features a co-packaged DDR2 DRAM chip, which needs its
timing param.
Add support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'arch/arm/mach-sunxi/dram_sunxi_dw.c')
| -rw-r--r-- | arch/arm/mach-sunxi/dram_sunxi_dw.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c index bd606ccc65..438b4740cd 100644 --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c @@ -340,6 +340,8 @@ static void mctl_set_cr(uint16_t socid, struct dram_para *para) writel(MCTL_CR_BL8 | MCTL_CR_INTERLEAVED | #if defined CONFIG_SUNXI_DRAM_DDR3 MCTL_CR_DDR3 | MCTL_CR_2T | +#elif defined CONFIG_SUNXI_DRAM_DDR2 + MCTL_CR_DDR2 | MCTL_CR_2T | #else #error Unsupported DRAM type! #endif |