diff options
| author | rick <rick@andestech.com> | 2017-08-29 05:12:02 +0300 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2017-09-21 05:30:22 +0300 |
| commit | e336b73d8ae06dbcc532d1833d7a5567babecca8 (patch) | |
| tree | 321b204124ad50381608dd5acc6ca8b1aa4b7892 /arch/nds32/cpu | |
| parent | ce4e2370f70f4bbd79e553dca73ec4439bfd567e (diff) | |
| download | u-boot-e336b73d8ae06dbcc532d1833d7a5567babecca8.tar.xz | |
nds32: ftmac100 support cache enable.
Enable cache and ftmac100 performance can be improved.
Signed-off-by: rick <rick@andestech.com>
Diffstat (limited to 'arch/nds32/cpu')
| -rw-r--r-- | arch/nds32/cpu/n1213/start.S | 29 |
1 files changed, 28 insertions, 1 deletions
diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S index f9f999902c..0d98d03fc3 100644 --- a/arch/nds32/cpu/n1213/start.S +++ b/arch/nds32/cpu/n1213/start.S @@ -119,19 +119,46 @@ set_ivb: /* set IVIC, vector size: 4 bytes, base: 0x0 */ mtsr $r0, $ivb /* - * MMU_CTL NTC0 Cacheable/Write-Back + * MMU_CTL NTC0 Non-cacheable */ + li $r0, ~0x6 + mfsr $r1, $mr0 + and $r1, $r1, $r0 + mtsr $r1, $mr0 + li $r0, ~0x3 mfsr $r1, $mr8 and $r1, $r1, $r0 mtsr $r1, $mr8 #if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)) +/* + * MMU_CTL NTC0 Cacheable/Write-Back + */ li $r0, 0x4 mfsr $r1, $mr0 or $r1, $r1, $r0 mtsr $r1, $mr0 #endif +#ifndef CONFIG_SYS_DCACHE_OFF +#ifdef CONFIG_ARCH_MAP_SYSMEM +/* + * MMU_CTL NTC1 Non-cacheable + */ + li $r0, ~0x18 + mfsr $r1, $mr0 + and $r1, $r1, $r0 + mtsr $r1, $mr0 +/* + * MMU_CTL NTM1 mapping for partition 0 + */ + li $r0, ~0x6000 + mfsr $r1, $mr0 + and $r1, $r1, $r0 + mtsr $r1, $mr0 +#endif +#endif + #if !defined(CONFIG_SYS_ICACHE_OFF) li $r0, 0x1 mfsr $r1, $mr8 |