diff options
author | Tom Rini <trini@konsulko.com> | 2016-11-30 03:42:48 +0300 |
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committer | Tom Rini <trini@konsulko.com> | 2016-11-30 03:42:48 +0300 |
commit | 6b29a395b62965eef6b5065d3a526a8588a92038 (patch) | |
tree | d9404d155aa96dd58ff9d02cdb2a30e7136405da /arch/powerpc/cpu | |
parent | dbd5df89d65172f94dec78af809f1e50dbd61fe6 (diff) | |
parent | e8a390f0189c5868f2fa305004821bcfcd71d32c (diff) | |
download | u-boot-6b29a395b62965eef6b5065d3a526a8588a92038.tar.xz |
Merge git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'arch/powerpc/cpu')
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/Kconfig | 321 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/Makefile | 103 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/b4860_ids.c | 4 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/b4860_serdes.c | 4 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/cmd_errata.c | 11 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu.c | 6 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu_init.c | 4 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu_init_early.c | 2 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/fdt.c | 13 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 2 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 6 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/pci.c | 2 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/speed.c | 36 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/start.S | 6 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/t2080_serdes.c | 4 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 4 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc86xx/Kconfig | 10 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc86xx/Makefile | 4 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc86xx/cpu.c | 6 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc86xx/speed.c | 2 |
20 files changed, 422 insertions, 128 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 9bcbda006d..3ee7d2f0c5 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -10,25 +10,37 @@ choice config TARGET_SBC8548 bool "Support sbc8548" + select ARCH_MPC8548 config TARGET_SOCRATES bool "Support socrates" + select ARCH_MPC8544 + +config TARGET_B4420QDS + bool "Support B4420QDS" + select ARCH_B4420 + select SUPPORT_SPL + select PHYS_64BIT config TARGET_B4860QDS bool "Support B4860QDS" + select ARCH_B4860 select SUPPORT_SPL select PHYS_64BIT config TARGET_BSC9131RDB bool "Support BSC9131RDB" + select ARCH_BSC9131 select SUPPORT_SPL config TARGET_BSC9132QDS bool "Support BSC9132QDS" + select ARCH_BSC9132 select SUPPORT_SPL config TARGET_C29XPCIE bool "Support C29XPCIE" + select ARCH_C29X select SUPPORT_SPL select SUPPORT_TPL select PHYS_64BIT @@ -36,135 +48,266 @@ config TARGET_C29XPCIE config TARGET_P3041DS bool "Support P3041DS" select PHYS_64BIT + select ARCH_P3041 config TARGET_P4080DS bool "Support P4080DS" select PHYS_64BIT + select ARCH_P4080 config TARGET_P5020DS bool "Support P5020DS" select PHYS_64BIT + select ARCH_P5020 config TARGET_P5040DS bool "Support P5040DS" select PHYS_64BIT + select ARCH_P5040 config TARGET_MPC8536DS bool "Support MPC8536DS" + select ARCH_MPC8536 config TARGET_MPC8540ADS bool "Support MPC8540ADS" + select ARCH_MPC8540 config TARGET_MPC8541CDS bool "Support MPC8541CDS" + select ARCH_MPC8541 config TARGET_MPC8544DS bool "Support MPC8544DS" + select ARCH_MPC8544 config TARGET_MPC8548CDS bool "Support MPC8548CDS" + select ARCH_MPC8548 config TARGET_MPC8555CDS bool "Support MPC8555CDS" + select ARCH_MPC8555 config TARGET_MPC8560ADS bool "Support MPC8560ADS" + select ARCH_MPC8560 config TARGET_MPC8568MDS bool "Support MPC8568MDS" + select ARCH_MPC8568 config TARGET_MPC8569MDS bool "Support MPC8569MDS" + select ARCH_MPC8569 config TARGET_MPC8572DS bool "Support MPC8572DS" + select ARCH_MPC8572 + +config TARGET_P1010RDB_PA + bool "Support P1010RDB_PA" + select ARCH_P1010 + select SUPPORT_SPL + select SUPPORT_TPL -config TARGET_P1010RDB - bool "Support P1010RDB" +config TARGET_P1010RDB_PB + bool "Support P1010RDB_PB" + select ARCH_P1010 select SUPPORT_SPL select SUPPORT_TPL config TARGET_P1022DS bool "Support P1022DS" + select ARCH_P1022 select SUPPORT_SPL select SUPPORT_TPL config TARGET_P1023RDB bool "Support P1023RDB" + select ARCH_P1023 + +config TARGET_P1020MBG + bool "Support P1020MBG-PC" + select SUPPORT_SPL + select SUPPORT_TPL + select ARCH_P1020 + +config TARGET_P1020RDB_PC + bool "Support P1020RDB-PC" + select SUPPORT_SPL + select SUPPORT_TPL + select ARCH_P1020 -config TARGET_P1_P2_RDB_PC - bool "Support p1_p2_rdb_pc" +config TARGET_P1020RDB_PD + bool "Support P1020RDB-PD" select SUPPORT_SPL select SUPPORT_TPL + select ARCH_P1020 + +config TARGET_P1020UTM + bool "Support P1020UTM" + select SUPPORT_SPL + select SUPPORT_TPL + select ARCH_P1020 + +config TARGET_P1021RDB + bool "Support P1021RDB" + select SUPPORT_SPL + select SUPPORT_TPL + select ARCH_P1021 + +config TARGET_P1024RDB + bool "Support P1024RDB" + select SUPPORT_SPL + select SUPPORT_TPL + select ARCH_P1024 + +config TARGET_P1025RDB + bool "Support P1025RDB" + select SUPPORT_SPL + select SUPPORT_TPL + select ARCH_P1025 + +config TARGET_P2020RDB + bool "Support P2020RDB-PC" + select SUPPORT_SPL + select SUPPORT_TPL + select ARCH_P2020 config TARGET_P1_TWR bool "Support p1_twr" + select ARCH_P1025 config TARGET_P2041RDB bool "Support P2041RDB" + select ARCH_P2041 select PHYS_64BIT config TARGET_QEMU_PPCE500 bool "Support qemu-ppce500" + select ARCH_QEMU_E500 select PHYS_64BIT -config TARGET_T102XQDS - bool "Support T102xQDS" +config TARGET_T1024QDS + bool "Support T1024QDS" + select ARCH_T1024 select SUPPORT_SPL select PHYS_64BIT -config TARGET_T102XRDB - bool "Support T102xRDB" +config TARGET_T1023RDB + bool "Support T1023RDB" + select ARCH_T1023 + select SUPPORT_SPL + select PHYS_64BIT + +config TARGET_T1024RDB + bool "Support T1024RDB" + select ARCH_T1024 select SUPPORT_SPL select PHYS_64BIT config TARGET_T1040QDS bool "Support T1040QDS" + select ARCH_T1040 + select PHYS_64BIT + +config TARGET_T1040RDB + bool "Support T1040RDB" + select ARCH_T1040 + select SUPPORT_SPL + select PHYS_64BIT + +config TARGET_T1040D4RDB + bool "Support T1040D4RDB" + select ARCH_T1040 + select SUPPORT_SPL + select PHYS_64BIT + +config TARGET_T1042RDB + bool "Support T1042RDB" + select ARCH_T1042 + select SUPPORT_SPL + select PHYS_64BIT + +config TARGET_T1042D4RDB + bool "Support T1042D4RDB" + select ARCH_T1042 + select SUPPORT_SPL + select PHYS_64BIT + +config TARGET_T1042RDB_PI + bool "Support T1042RDB_PI" + select ARCH_T1042 + select SUPPORT_SPL select PHYS_64BIT -config TARGET_T104XRDB - bool "Support T104xRDB" +config TARGET_T2080QDS + bool "Support T2080QDS" + select ARCH_T2080 select SUPPORT_SPL select PHYS_64BIT -config TARGET_T208XQDS - bool "Support T208xQDS" +config TARGET_T2080RDB + bool "Support T2080RDB" + select ARCH_T2080 select SUPPORT_SPL select PHYS_64BIT -config TARGET_T208XRDB - bool "Support T208xRDB" +config TARGET_T2081QDS + bool "Support T2081QDS" + select ARCH_T2081 + select SUPPORT_SPL + select PHYS_64BIT + +config TARGET_T4160QDS + bool "Support T4160QDS" + select ARCH_T4160 + select SUPPORT_SPL + select PHYS_64BIT + +config TARGET_T4160RDB + bool "Support T4160RDB" + select ARCH_T4160 select SUPPORT_SPL select PHYS_64BIT config TARGET_T4240QDS bool "Support T4240QDS" + select ARCH_T4240 select SUPPORT_SPL select PHYS_64BIT config TARGET_T4240RDB bool "Support T4240RDB" + select ARCH_T4240 select SUPPORT_SPL select PHYS_64BIT config TARGET_CONTROLCENTERD bool "Support controlcenterd" + select ARCH_P1022 config TARGET_KMP204X bool "Support kmp204x" + select ARCH_P2041 select PHYS_64BIT config TARGET_XPEDITE520X bool "Support xpedite520x" + select ARCH_MPC8548 config TARGET_XPEDITE537X bool "Support xpedite537x" + select ARCH_MPC8572 config TARGET_XPEDITE550X bool "Support xpedite550x" + select ARCH_P2020 config TARGET_UCP1020 bool "Support uCP1020" + select ARCH_P1020 config TARGET_CYRUS bool "Support Varisys Cyrus" @@ -172,6 +315,156 @@ config TARGET_CYRUS endchoice +config ARCH_B4420 + bool + +config ARCH_B4860 + bool + +config ARCH_BSC9131 + bool + +config ARCH_BSC9132 + bool + +config ARCH_C29X + bool + +config ARCH_MPC8536 + bool + +config ARCH_MPC8540 + bool + +config ARCH_MPC8541 + bool + +config ARCH_MPC8544 + bool + +config ARCH_MPC8548 + bool + +config ARCH_MPC8555 + bool + +config ARCH_MPC8560 + bool + +config ARCH_MPC8568 + bool + +config ARCH_MPC8569 + bool + +config ARCH_MPC8572 + bool + +config ARCH_P1010 + bool + +config ARCH_P1011 + bool + +config ARCH_P1020 + bool + +config ARCH_P1021 + bool + +config ARCH_P1022 + bool + +config ARCH_P1023 + bool + +config ARCH_P1024 + bool + +config ARCH_P1025 + bool + +config ARCH_P2020 + bool + +config ARCH_P2041 + bool + +config ARCH_P3041 + bool + +config ARCH_P4080 + bool + +config ARCH_P5020 + bool + +config ARCH_P5040 + bool + +config ARCH_QEMU_E500 + bool + +config ARCH_T1023 + bool + +config ARCH_T1024 + bool + +config ARCH_T1040 + bool + +config ARCH_T1042 + bool + +config ARCH_T2080 + bool + +config ARCH_T2081 + bool + +config ARCH_T4160 + bool + +config ARCH_T4240 + bool + +config MAX_CPUS + int "Maximum number of CPUs permitted for MPC85xx" + default 12 if ARCH_T4240 + default 8 if ARCH_P4080 || \ + ARCH_T4160 + default 4 if ARCH_B4860 || \ + ARCH_P2041 || \ + ARCH_P3041 || \ + ARCH_P5040 || \ + ARCH_T1040 || \ + ARCH_T1042 || \ + ARCH_T2080 || \ + ARCH_T2081 + default 2 if ARCH_B4420 || \ + ARCH_BSC9132 || \ + ARCH_MPC8572 || \ + ARCH_P1020 || \ + ARCH_P1021 || \ + ARCH_P1022 || \ + ARCH_P1023 || \ + ARCH_P1024 || \ + ARCH_P1025 || \ + ARCH_P2020 || \ + ARCH_P5020 || \ + ARCH_T1020 || \ + ARCH_T1022 || \ + ARCH_T1023 || \ + ARCH_T1024 + default 1 + help + Set this number to the maximum number of possible CPUs in the SoC. + SoCs may have multiple clusters with each cluster may have multiple + ports. If some ports are reserved but higher ports are used for + cores, count the reserved ports. This will allocate enough memory + in spin table to properly handle all cores. + source "board/freescale/b4860qds/Kconfig" source "board/freescale/bsc9131rdb/Kconfig" source "board/freescale/bsc9132qds/Kconfig" diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index f4c4fe2602..46ed22cafc 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -39,24 +39,23 @@ obj-$(CONFIG_PCI) += pci.o obj-$(CONFIG_SYS_DPAA_QBMAN) += portals.o # various SoC specific assignments -obj-$(CONFIG_PPC_P2041) += p2041_ids.o -obj-$(CONFIG_PPC_P3041) += p3041_ids.o -obj-$(CONFIG_PPC_P4080) += p4080_ids.o -obj-$(CONFIG_PPC_P5020) += p5020_ids.o -obj-$(CONFIG_PPC_P5040) += p5040_ids.o -obj-$(CONFIG_PPC_T4240) += t4240_ids.o -obj-$(CONFIG_PPC_T4160) += t4240_ids.o -obj-$(CONFIG_PPC_T4080) += t4240_ids.o -obj-$(CONFIG_PPC_B4420) += b4860_ids.o -obj-$(CONFIG_PPC_B4860) += b4860_ids.o -obj-$(CONFIG_PPC_T1040) += t1040_ids.o -obj-$(CONFIG_PPC_T1042) += t1040_ids.o +obj-$(CONFIG_ARCH_P2041) += p2041_ids.o +obj-$(CONFIG_ARCH_P3041) += p3041_ids.o +obj-$(CONFIG_ARCH_P4080) += p4080_ids.o +obj-$(CONFIG_ARCH_P5020) += p5020_ids.o +obj-$(CONFIG_ARCH_P5040) += p5040_ids.o +obj-$(CONFIG_ARCH_T4240) += t4240_ids.o +obj-$(CONFIG_ARCH_T4160) += t4240_ids.o +obj-$(CONFIG_ARCH_B4420) += b4860_ids.o +obj-$(CONFIG_ARCH_B4860) += b4860_ids.o +obj-$(CONFIG_ARCH_T1040) += t1040_ids.o +obj-$(CONFIG_ARCH_T1042) += t1040_ids.o obj-$(CONFIG_PPC_T1020) += t1040_ids.o obj-$(CONFIG_PPC_T1022) += t1040_ids.o -obj-$(CONFIG_PPC_T1023) += t1024_ids.o -obj-$(CONFIG_PPC_T1024) += t1024_ids.o -obj-$(CONFIG_PPC_T2080) += t2080_ids.o -obj-$(CONFIG_PPC_T2081) += t2080_ids.o +obj-$(CONFIG_ARCH_T1023) += t1024_ids.o +obj-$(CONFIG_ARCH_T1024) += t1024_ids.o +obj-$(CONFIG_ARCH_T2080) += t2080_ids.o +obj-$(CONFIG_ARCH_T2081) += t2080_ids.o obj-$(CONFIG_QE) += qe_io.o @@ -65,52 +64,46 @@ obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o # SoC specific SERDES support -obj-$(CONFIG_PPC_C29X) += c29x_serdes.o -obj-$(CONFIG_MPC8536) += mpc8536_serdes.o -obj-$(CONFIG_MPC8544) += mpc8544_serdes.o -obj-$(CONFIG_MPC8548) += mpc8548_serdes.o -obj-$(CONFIG_MPC8568) += mpc8568_serdes.o -obj-$(CONFIG_MPC8569) += mpc8569_serdes.o -obj-$(CONFIG_MPC8572) += mpc8572_serdes.o -obj-$(CONFIG_P1010) += p1010_serdes.o -obj-$(CONFIG_P1011) += p1021_serdes.o -obj-$(CONFIG_P1012) += p1021_serdes.o -obj-$(CONFIG_P1013) += p1022_serdes.o -obj-$(CONFIG_P1014) += p1010_serdes.o -obj-$(CONFIG_P1017) += p1023_serdes.o -obj-$(CONFIG_P1020) += p1021_serdes.o -obj-$(CONFIG_P1021) += p1021_serdes.o -obj-$(CONFIG_P1022) += p1022_serdes.o -obj-$(CONFIG_P1023) += p1023_serdes.o -obj-$(CONFIG_P1024) += p1021_serdes.o -obj-$(CONFIG_P1025) += p1021_serdes.o -obj-$(CONFIG_P2010) += p2020_serdes.o -obj-$(CONFIG_P2020) += p2020_serdes.o -obj-$(CONFIG_PPC_P2041) += p2041_serdes.o -obj-$(CONFIG_PPC_P3041) += p3041_serdes.o -obj-$(CONFIG_PPC_P4080) += p4080_serdes.o -obj-$(CONFIG_PPC_P5020) += p5020_serdes.o -obj-$(CONFIG_PPC_P5040) += p5040_serdes.o -obj-$(CONFIG_PPC_T4240) += t4240_serdes.o -obj-$(CONFIG_PPC_T4160) += t4240_serdes.o -obj-$(CONFIG_PPC_T4080) += t4240_serdes.o -obj-$(CONFIG_PPC_B4420) += b4860_serdes.o -obj-$(CONFIG_PPC_B4860) += b4860_serdes.o -obj-$(CONFIG_BSC9132) += bsc9132_serdes.o -obj-$(CONFIG_PPC_T1040) += t1040_serdes.o -obj-$(CONFIG_PPC_T1042) += t1040_serdes.o +obj-$(CONFIG_ARCH_C29X) += c29x_serdes.o +obj-$(CONFIG_ARCH_MPC8536) += mpc8536_serdes.o +obj-$(CONFIG_ARCH_MPC8544) += mpc8544_serdes.o +obj-$(CONFIG_ARCH_MPC8548) += mpc8548_serdes.o +obj-$(CONFIG_ARCH_MPC8568) += mpc8568_serdes.o +obj-$(CONFIG_ARCH_MPC8569) += mpc8569_serdes.o +obj-$(CONFIG_ARCH_MPC8572) += mpc8572_serdes.o +obj-$(CONFIG_ARCH_P1010) += p1010_serdes.o +obj-$(CONFIG_ARCH_P1011) += p1021_serdes.o +obj-$(CONFIG_ARCH_P1020) += p1021_serdes.o +obj-$(CONFIG_ARCH_P1021) += p1021_serdes.o +obj-$(CONFIG_ARCH_P1022) += p1022_serdes.o +obj-$(CONFIG_ARCH_P1023) += p1023_serdes.o +obj-$(CONFIG_ARCH_P1024) += p1021_serdes.o +obj-$(CONFIG_ARCH_P1025) += p1021_serdes.o +obj-$(CONFIG_ARCH_P2020) += p2020_serdes.o +obj-$(CONFIG_ARCH_P2041) += p2041_serdes.o +obj-$(CONFIG_ARCH_P3041) += p3041_serdes.o +obj-$(CONFIG_ARCH_P4080) += p4080_serdes.o +obj-$(CONFIG_ARCH_P5020) += p5020_serdes.o +obj-$(CONFIG_ARCH_P5040) += p5040_serdes.o +obj-$(CONFIG_ARCH_T4240) += t4240_serdes.o +obj-$(CONFIG_ARCH_T4160) += t4240_serdes.o +obj-$(CONFIG_ARCH_B4420) += b4860_serdes.o +obj-$(CONFIG_ARCH_B4860) += b4860_serdes.o +obj-$(CONFIG_ARCH_BSC9132) += bsc9132_serdes.o +obj-$(CONFIG_ARCH_T1040) += t1040_serdes.o +obj-$(CONFIG_ARCH_T1042) += t1040_serdes.o obj-$(CONFIG_PPC_T1020) += t1040_serdes.o obj-$(CONFIG_PPC_T1022) += t1040_serdes.o -obj-$(CONFIG_PPC_T1023) += t1024_serdes.o -obj-$(CONFIG_PPC_T1024) += t1024_serdes.o -obj-$(CONFIG_PPC_T2080) += t2080_serdes.o -obj-$(CONFIG_PPC_T2081) += t2080_serdes.o +obj-$(CONFIG_ARCH_T1023) += t1024_serdes.o +obj-$(CONFIG_ARCH_T1024) += t1024_serdes.o +obj-$(CONFIG_ARCH_T2080) += t2080_serdes.o +obj-$(CONFIG_ARCH_T2081) += t2080_serdes.o obj-y += cpu.o obj-y += cpu_init.o obj-y += cpu_init_early.o obj-y += interrupts.o -ifneq ($(CONFIG_QEMU_E500),y) +ifneq ($(CONFIG_ARCH_QEMU_E500),y) obj-y += speed.o endif obj-y += tlb.o diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c index 85eba0b22d..4ceb6f51f3 100644 --- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c +++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c @@ -62,7 +62,7 @@ struct liodn_id_table liodn_tbl[] = { SET_DMA_LIODN(1, "fsl,elo3-dma", 147), SET_DMA_LIODN(2, "fsl,elo3-dma", 227), -#ifndef CONFIG_PPC_B4420 +#ifndef CONFIG_ARCH_B4420 SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), @@ -81,7 +81,7 @@ struct fman_liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 3, 91), SET_FMAN_RX_1G_LIODN(1, 4, 92), SET_FMAN_RX_1G_LIODN(1, 5, 93), -#ifndef CONFIG_PPC_B4420 +#ifndef CONFIG_ARCH_B4420 SET_FMAN_RX_10G_LIODN(1, 0, 94), SET_FMAN_RX_10G_LIODN(1, 1, 95), #endif diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c index 63172def68..a5709dddc0 100644 --- a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c @@ -15,7 +15,7 @@ struct serdes_config { u8 lanes[SRDS_MAX_LANES]; }; -#ifdef CONFIG_PPC_B4860 +#ifdef CONFIG_ARCH_B4860 static struct serdes_config serdes1_cfg_tbl[] = { /* SerDes 1 */ {0x01, {AURORA, AURORA, CPRI6, CPRI5, @@ -180,7 +180,7 @@ static struct serdes_config serdes2_cfg_tbl[] = { }; #endif -#ifdef CONFIG_PPC_B4420 +#ifdef CONFIG_ARCH_B4420 static struct serdes_config serdes1_cfg_tbl[] = { {0x0D, {NONE, NONE, CPRI6, CPRI5, CPRI4, CPRI3, NONE, NONE} }, diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 3b06ae42e4..402a1ff33c 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -26,12 +26,12 @@ static void check_erratum_a4849(uint32_t svr) void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000; unsigned int i; -#if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041) +#if defined(CONFIG_ARCH_P2041) || defined(CONFIG_ARCH_P3041) static const uint8_t offsets[] = { 0x50, 0x54, 0x58, 0x90, 0x94, 0x98 }; #endif -#ifdef CONFIG_PPC_P4080 +#ifdef CONFIG_ARCH_P4080 static const uint8_t offsets[] = { 0x60, 0x64, 0x68, 0x6c, 0xa0, 0xa4, 0xa8, 0xac }; @@ -45,11 +45,11 @@ static void check_erratum_a4849(uint32_t svr) } } -#if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041) +#if defined(CONFIG_ARCH_P2041) || defined(CONFIG_ARCH_P3041) x108 = 0x12; #endif -#ifdef CONFIG_PPC_P4080 +#ifdef CONFIG_ARCH_P4080 /* * For P4080, the erratum document says that the value at offset 0x108 * should be 0x12 on rev2, or 0x1c on rev3. @@ -323,7 +323,8 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (IS_SVR_REV(svr, 1, 0)) puts("Work-around for Erratum A-008044 enabled\n"); #endif -#if defined(CONFIG_SYS_FSL_B4860QDS_XFI_ERR) && defined(CONFIG_B4860QDS) +#if defined(CONFIG_SYS_FSL_B4860QDS_XFI_ERR) && \ + (defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS)) puts("Work-around for Erratum XFI on B4860QDS enabled\n"); #endif #ifdef CONFIG_SYS_FSL_ERRATUM_A009663 diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index cabf64cf8c..d180c73929 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -293,8 +293,8 @@ int checkcpu (void) int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { /* Everything after the first generation of PQ3 parts has RSTCR */ -#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ - defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) +#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \ + defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8560) unsigned long val, msr; /* @@ -404,7 +404,7 @@ void mpc85xx_reginfo(void) phys_size_t initdram(int board_type) { #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \ - defined(CONFIG_QEMU_E500) + defined(CONFIG_ARCH_QEMU_E500) return fsl_ddr_sdram_size(); #else return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 53b3729f98..c2402a8bda 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -442,7 +442,7 @@ ulong cpu_init_f(void) #if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT) struct law_entry law; #endif -#ifdef CONFIG_MPC8548 +#ifdef CONFIG_ARCH_MPC8548 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); uint svr = get_svr(); @@ -959,7 +959,7 @@ int cpu_init_r(void) #ifdef CONFIG_FSL_CAAM sec_init(); -#if defined(CONFIG_PPC_C29X) +#if defined(CONFIG_ARCH_C29X) if ((SVR_SOC_VER(svr) == SVR_C292) || (SVR_SOC_VER(svr) == SVR_C293)) sec_init_idx(1); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index aa519b03fe..345d693ec4 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -97,7 +97,7 @@ void cpu_init_early_f(void *fdt) /* gd area was zeroed during startup */ -#ifdef CONFIG_QEMU_E500 +#ifdef CONFIG_ARCH_QEMU_E500 /* * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems, * so we need to populate it before it accesses it. diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 047c972ac7..12001f85e9 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -490,7 +490,7 @@ static void ft_fixup_qe_snum(void *blob) } #endif -#if defined(CONFIG_PPC_P4080) +#if defined(CONFIG_ARCH_P4080) static void fdt_fixup_usb(void *fdt) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -511,8 +511,8 @@ static void fdt_fixup_usb(void *fdt) #define fdt_fixup_usb(x) #endif -#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T4240) || \ - defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080) +#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240) || \ + defined(CONFIG_ARCH_T4160) void fdt_fixup_dma3(void *blob) { /* the 3rd DMA is not functional if SRIO2 is chosen */ @@ -520,7 +520,7 @@ void fdt_fixup_dma3(void *blob) ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300) -#if defined(CONFIG_PPC_T2080) +#if defined(CONFIG_ARCH_T2080) u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL; srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; @@ -529,8 +529,7 @@ void fdt_fixup_dma3(void *blob) case 0x29: case 0x2d: case 0x2e: -#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ - defined(CONFIG_PPC_T4080) +#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS4_PRTCL; srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT; @@ -556,7 +555,7 @@ void fdt_fixup_dma3(void *blob) #define fdt_fixup_dma3(x) #endif -#if defined(CONFIG_PPC_T1040) +#if defined(CONFIG_ARCH_T1040) static void fdt_fixup_l2_switch(void *blob) { uchar l2swaddr[6]; diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c index 810ddb0867..677b062044 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -391,7 +391,7 @@ const char *serdes_clock_to_string(u32 clock) case SRDS_PLLCR0_RFCK_SEL_161_13: return "161.1328123"; default: -#if defined(CONFIG_T4240QDS) +#if defined(CONFIG_TARGET_T4240QDS) || defined(CONFIG_TARGET_T4160QDS) return "???"; #else return "122.88"; diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index b6c4341544..1bc0c64cfc 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -76,7 +76,7 @@ static const struct { { 17, 163, FSL_SRDS_BANK_2 }, { 18, 164, FSL_SRDS_BANK_2 }, { 19, 165, FSL_SRDS_BANK_2 }, -#ifdef CONFIG_PPC_P4080 +#ifdef CONFIG_ARCH_P4080 { 20, 170, FSL_SRDS_BANK_3 }, { 21, 171, FSL_SRDS_BANK_3 }, { 22, 172, FSL_SRDS_BANK_3 }, @@ -491,7 +491,7 @@ void fsl_serdes_init(void) ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int cfg; serdes_corenet_t *srds_regs; -#ifdef CONFIG_PPC_P5040 +#ifdef CONFIG_ARCH_P5040 serdes_corenet_t *srds2_regs; #endif int lane, bank, idx; @@ -577,7 +577,7 @@ void fsl_serdes_init(void) } } -#ifdef CONFIG_PPC_P5040 +#ifdef CONFIG_ARCH_P5040 /* * Lanes on bank 4 on P5040 are commented-out, but for some SERDES * protocols, these lanes are routed to SATA. We use serdes_prtcl_map diff --git a/arch/powerpc/cpu/mpc85xx/pci.c b/arch/powerpc/cpu/mpc85xx/pci.c index c6d2fda5db..538729f388 100644 --- a/arch/powerpc/cpu/mpc85xx/pci.c +++ b/arch/powerpc/cpu/mpc85xx/pci.c @@ -120,7 +120,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose) pci_register_hose(hose); -#if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS) +#if defined(CONFIG_TARGET_MPC8555CDS) || defined(CONFIG_TARGET_MPC8541CDS) /* * This is a SW workaround for an apparent HW problem * in the PCI controller on the MPC85555/41 CDS boards. diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index e732969e41..fcf5d92af5 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -130,9 +130,8 @@ void get_sys_info(sys_info_t *sys_info) * it uses 6. * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0 */ -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ - defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080) || \ - defined(CONFIG_PPC_T2081) +#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \ + defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) svr = get_svr(); switch (SVR_SOC_VER(svr)) { case SVR_T4240: @@ -202,11 +201,11 @@ void get_sys_info(sys_info_t *sys_info) } #endif -#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) || \ - defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) +#if defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) || \ + defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) #define FM1_CLK_SEL 0xe0000000 #define FM1_CLK_SHIFT 29 -#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) +#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) #define FM1_CLK_SEL 0x00000007 #define FM1_CLK_SHIFT 0 #else @@ -216,7 +215,7 @@ void get_sys_info(sys_info_t *sys_info) #define FM1_CLK_SHIFT 26 #endif #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) -#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) +#if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) rcw_tmp = in_be32(&gur->rcwsr[15]) - 4; #else rcw_tmp = in_be32(&gur->rcwsr[7]); @@ -456,7 +455,7 @@ void get_sys_info(sys_info_t *sys_info) #endif #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK -#if defined(CONFIG_PPC_T2080) +#if defined(CONFIG_ARCH_T2080) #define ESDHC_CLK_SEL 0x00000007 #define ESDHC_CLK_SHIFT 0 #define ESDHC_CLK_RCWSR 15 @@ -480,7 +479,7 @@ void get_sys_info(sys_info_t *sys_info) case 4: sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 4; break; -#if defined(CONFIG_PPC_T2080) +#if defined(CONFIG_ARCH_T2080) case 5: sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK]; break; @@ -596,7 +595,7 @@ void get_sys_info(sys_info_t *sys_info) #endif #ifdef CONFIG_QE -#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) +#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) sys_info->freq_qe = sys_info->freq_systembus; #else qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) @@ -625,8 +624,8 @@ void get_sys_info(sys_info_t *sys_info) * for four times the clock divider values. */ lcrr_div *= 4; -#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \ - !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560) +#elif !defined(CONFIG_ARCH_MPC8540) && !defined(CONFIG_ARCH_MPC8541) && \ + !defined(CONFIG_ARCH_MPC8555) && !defined(CONFIG_ARCH_MPC8560) /* * Yes, the entire PQ38 family use the same * bit-representation for twice the clock divider values. @@ -652,7 +651,7 @@ void get_sys_info(sys_info_t *sys_info) int get_clocks (void) { sys_info_t sys_info; -#ifdef CONFIG_MPC8544 +#ifdef CONFIG_ARCH_MPC8544 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR; #endif #if defined(CONFIG_CPM2) @@ -681,11 +680,11 @@ int get_clocks (void) * for that SOC. This information is taken from application note * AN2919. */ -#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ - defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \ - defined(CONFIG_P1022) +#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \ + defined(CONFIG_ARCH_MPC8560) || defined(CONFIG_ARCH_MPC8555) || \ + defined(CONFIG_ARCH_P1022) gd->arch.i2c1_clk = sys_info.freq_systembus; -#elif defined(CONFIG_MPC8544) +#elif defined(CONFIG_ARCH_MPC8544) /* * On the 8544, the I2C clock is the same as the SEC clock. This can be * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See @@ -707,8 +706,7 @@ int get_clocks (void) #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK gd->arch.sdhc_clk = sys_info.freq_sdhc / 2; #else -#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\ - defined(CONFIG_P1014) +#if defined(CONFIG_ARCH_MPC8569) || defined(CONFIG_ARCH_P1010) gd->arch.sdhc_clk = gd->bus_clk; #else gd->arch.sdhc_clk = gd->bus_clk / 2; diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index c3e12349f7..932216c237 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -311,7 +311,7 @@ l2_disabled: #endif mtspr HID0,r0 -#if !defined(CONFIG_E500MC) && !defined(CONFIG_QEMU_E500) +#if !defined(CONFIG_E500MC) && !defined(CONFIG_ARCH_QEMU_E500) li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ mfspr r3,PVR andi. r3,r3, 0xff @@ -345,7 +345,7 @@ l2_disabled: mtspr DBCR0,r0 #endif -#ifdef CONFIG_MPC8569 +#ifdef CONFIG_ARCH_MPC8569 #define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000) #define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0) @@ -376,7 +376,7 @@ l2_disabled: tlbivax 0,r4 isync -#endif /* CONFIG_MPC8569 */ +#endif /* CONFIG_ARCH_MPC8569 */ /* * Search for the TLB that covers the code we're executing, and shrink it diff --git a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c index c65f41d0f8..fc63fe3613 100644 --- a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c @@ -161,7 +161,7 @@ static const struct serdes_config serdes1_cfg_tbl[] = { {} }; -#ifndef CONFIG_PPC_T2081 +#ifndef CONFIG_ARCH_T2081 static const struct serdes_config serdes2_cfg_tbl[] = { /* SerDes 2 */ {0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} }, @@ -181,7 +181,7 @@ static const struct serdes_config serdes2_cfg_tbl[] = { static const struct serdes_config *serdes_cfg_tbl[] = { serdes1_cfg_tbl, -#ifndef CONFIG_PPC_T2081 +#ifndef CONFIG_ARCH_T2081 serdes2_cfg_tbl, #endif }; diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c index 7b43b282bb..3fc527d375 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c @@ -15,7 +15,7 @@ struct serdes_config { u8 lanes[SRDS_MAX_LANES]; }; -#ifdef CONFIG_PPC_T4240 +#ifdef CONFIG_ARCH_T4240 static const struct serdes_config serdes1_cfg_tbl[] = { /* SerDes 1 */ {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, @@ -263,7 +263,7 @@ static const struct serdes_config serdes4_cfg_tbl[] = { {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}}, {} }; -#elif defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080) +#elif defined(CONFIG_ARCH_T4160) static const struct serdes_config serdes1_cfg_tbl[] = { /* SerDes 1 */ {1, {NONE, NONE, NONE, NONE, diff --git a/arch/powerpc/cpu/mpc86xx/Kconfig b/arch/powerpc/cpu/mpc86xx/Kconfig index fe1859d206..98fb702e86 100644 --- a/arch/powerpc/cpu/mpc86xx/Kconfig +++ b/arch/powerpc/cpu/mpc86xx/Kconfig @@ -10,18 +10,28 @@ choice config TARGET_SBC8641D bool "Support sbc8641d" + select ARCH_MPC8641 config TARGET_MPC8610HPCD bool "Support MPC8610HPCD" + select ARCH_MPC8610 config TARGET_MPC8641HPCN bool "Support MPC8641HPCN" + select ARCH_MPC8641 config TARGET_XPEDITE517X bool "Support xpedite517x" + select ARCH_MPC8641 endchoice +config ARCH_MPC8610 + bool + +config ARCH_MPC8641 + bool + source "board/freescale/mpc8610hpcd/Kconfig" source "board/freescale/mpc8641hpcn/Kconfig" source "board/sbc8641d/Kconfig" diff --git a/arch/powerpc/cpu/mpc86xx/Makefile b/arch/powerpc/cpu/mpc86xx/Makefile index 0f790b0efc..88c23fc58c 100644 --- a/arch/powerpc/cpu/mpc86xx/Makefile +++ b/arch/powerpc/cpu/mpc86xx/Makefile @@ -19,6 +19,6 @@ obj-y += cpu_init.o obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-y += interrupts.o obj-$(CONFIG_MP) += mp.o -obj-$(CONFIG_MPC8610) += mpc8610_serdes.o -obj-$(CONFIG_MPC8641) += mpc8641_serdes.o +obj-$(CONFIG_ARCH_MPC8610) += mpc8610_serdes.o +obj-$(CONFIG_ARCH_MPC8641) += mpc8641_serdes.o obj-y += speed.o diff --git a/arch/powerpc/cpu/mpc86xx/cpu.c b/arch/powerpc/cpu/mpc86xx/cpu.c index 30518544dd..7a9570c8ec 100644 --- a/arch/powerpc/cpu/mpc86xx/cpu.c +++ b/arch/powerpc/cpu/mpc86xx/cpu.c @@ -90,9 +90,9 @@ checkcpu(void) puts("L2: "); if (get_l2cr() & 0x80000000) { -#if defined(CONFIG_MPC8610) +#if defined(CONFIG_ARCH_MPC8610) puts("256"); -#elif defined(CONFIG_MPC8641) +#elif defined(CONFIG_ARCH_MPC8641) puts("512"); #endif puts(" KiB enabled\n"); @@ -139,7 +139,7 @@ get_tbclk(void) void watchdog_reset(void) { -#if defined(CONFIG_MPC8610) +#if defined(CONFIG_ARCH_MPC8610) /* * This actually feed the hard enabled watchdog. */ diff --git a/arch/powerpc/cpu/mpc86xx/speed.c b/arch/powerpc/cpu/mpc86xx/speed.c index 5abe6f0bf2..05f23db457 100644 --- a/arch/powerpc/cpu/mpc86xx/speed.c +++ b/arch/powerpc/cpu/mpc86xx/speed.c @@ -115,7 +115,7 @@ int get_clocks(void) * for that SOC. This information is taken from application note * AN2919. */ -#ifdef CONFIG_MPC8610 +#ifdef CONFIG_ARCH_MPC8610 gd->arch.i2c1_clk = sys_info.freq_systembus; #else gd->arch.i2c1_clk = sys_info.freq_systembus / 2; |