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| author | Bin Meng <bmeng.cn@gmail.com> | 2021-06-04 08:51:12 +0300 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2021-06-17 04:39:08 +0300 |
| commit | 048aff6d2621df2654dce6f833a2cf843358486a (patch) | |
| tree | daf0055c9f961f0a3dad8f9139e328364307bf10 /arch/riscv/dts/ae350_64.dts | |
| parent | f050dd2b26abb4b107c3cdf7a5f5c420a9e1d4b6 (diff) | |
| download | u-boot-048aff6d2621df2654dce6f833a2cf843358486a.tar.xz | |
riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit
All the device nodes that refer to plic0 as their interrupt parent
have 2 cells encoded in their interrupts property, but plic0 only
provides 1 cell in #interrupt-cells which is incorrect.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'arch/riscv/dts/ae350_64.dts')
0 files changed, 0 insertions, 0 deletions