diff options
| author | Simon Glass <sjg@chromium.org> | 2019-12-07 07:42:26 +0300 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2019-12-15 06:44:18 +0300 |
| commit | 86a8fb3b3b45523744d23626e419f72b7e201da8 (patch) | |
| tree | f573c4b298d994e7d64e8ee8ced49c1b181148b6 /arch/x86/dts | |
| parent | f45e747d6d0b107992e8aed74c001034c8a6f1a1 (diff) | |
| download | u-boot-86a8fb3b3b45523744d23626e419f72b7e201da8.tar.xz | |
x86: Disable microcode section for FSP2
At present we don't support loading microcode with FSP2. The correct way
to do this is by adding it to the FIT. For now, disable including
microcode in the image.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/dts')
| -rw-r--r-- | arch/x86/dts/u-boot.dtsi | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index 33441c7c80..850fe3ac11 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -37,11 +37,13 @@ }; #endif #ifdef CONFIG_TPL +#ifdef CONFIG_HAVE_MICROCODE u-boot-tpl-with-ucode-ptr { offset = <CONFIG_TPL_TEXT_BASE>; }; u-boot-tpl-dtb { }; +#endif u-boot-spl { offset = <CONFIG_SPL_TEXT_BASE>; }; @@ -77,11 +79,16 @@ offset = <CONFIG_SYS_TEXT_BASE>; }; #endif +#ifdef CONFIG_HAVE_MICROCODE u-boot-dtb-with-ucode { }; u-boot-ucode { align = <16>; }; +#else + u-boot-dtb { + }; +#endif #ifdef CONFIG_HAVE_X86_FIT intel-fit { }; |