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| author | Yan Hong Wang <yanhongwang@linux.starfivetech.com> | 2022-09-23 10:16:40 +0300 |
|---|---|---|
| committer | Yanhong Wang <yanhong.wang@linux.starfivetech.com> | 2022-10-18 11:24:38 +0300 |
| commit | 7efb109f1dd2f9a34da35392338ba3290764ec5c (patch) | |
| tree | 9fcba70f103b33741fe82682be371e1b3ae3f5a9 /arch | |
| parent | 6c18803bcb898acd1f983315e9063209ba1d13e8 (diff) | |
| download | u-boot-7efb109f1dd2f9a34da35392338ba3290764ec5c.tar.xz | |
riscv: dts: jh7110: Add reset property to DDR control node
Add reset property configuration to DDR control device tree node.
Signed-off-by: Yan Hong Wang <yanhongwang@linux.starfivetech.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/riscv/dts/jh7110-u-boot.dtsi | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi index 2b5cdee19d..21a14bdc4d 100644 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -59,8 +59,12 @@ }; dmc: dmc@100b0000 { - compatible = "starfive,jh7110-ddr"; + compatible = "starfive,jh7110-dmc"; reg = <0x0 0x15700000 0x0 0x10000 0x0 0x13000000 0x0 0x10000>; + resets = <&rstgen RSTN_U0_DDR_AXI>, + <&rstgen RSTN_U0_DDR_OSC>, + <&rstgen RSTN_U0_DDR_APB>; + reset-names = "axi", "osc", "apb"; clock-frequency = <2133>; u-boot,dm-spl; }; |