riscv: dts: starfive: Enable PCIe host controller

Enable and add pinctrl configuration for PCIe host controller.

Signed-off-by: Mason Huo <mason.huo@starfivetech.com>

2 files changed, 114 insertions, 12 deletions

diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index 485b9053d0..9e5b0576f9 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -1186,17 +1186,18 @@
 		};
 
 		pcie0: pcie@2B000000 {
-			compatible = "plda,pci-xpressrich3-axi";
+			compatible = "starfive,jh7110-pcie";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			#interrupt-cells = <1>;
-			reg = <0x0 0x2B000000 0x0 0x1000000
-			       0x9 0x40000000 0x0 0x10000000>;
+			reg = <0x0 0x2B000000 0x0 0x1000000>,
+			      <0x9 0x40000000 0x0 0x10000000>;
 			reg-names = "reg", "config";
 			device_type = "pci";
 			starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>;
 			bus-range = <0x0 0xff>;
-			ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x06000000>;
+			ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x08000000>,
+				<0xc3000000  0x9 0x00000000  0x9 0x00000000 0x0 0x40000000>;
 			msi-parent = <&plic>;
 			interrupts = <56>;
 			interrupt-controller;
@@ -1215,25 +1216,27 @@
 				 <&rstgen RSTN_U0_PLDA_PCIE_APB>;
 			reset-names = "rst_mst0", "rst_slv0", "rst_slv",
 				      "rst_brg", "rst_core", "rst_apb";
-			clocks = <&clkgen JH7110_PCIE0_CLK_TL>,
+			clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
+				 <&clkgen JH7110_PCIE0_CLK_TL>,
 				 <&clkgen JH7110_PCIE0_CLK_AXI_MST0>,
 				 <&clkgen JH7110_PCIE0_CLK_APB>;
-			clock-names =  "tl", "axi_mst0", "apb";
+			clock-names = "noc", "tl", "axi_mst0", "apb";
 			status = "disabled";
 		};
 
 		pcie1: pcie@2C000000 {
-			compatible = "plda,pci-xpressrich3-axi";
+			compatible = "starfive,jh7110-pcie";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			#interrupt-cells = <1>;
-			reg = <0x0 0x2C000000 0x0 0x1000000
-			       0x9 0xc0000000 0x0 0x10000000>;
+			reg = <0x0 0x2C000000 0x0 0x1000000>,
+			      <0x9 0xc0000000 0x0 0x10000000>;
 			reg-names = "reg", "config";
 			device_type = "pci";
 			starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0>;
 			bus-range = <0x0 0xff>;
-			ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x06000000>;
+			ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x08000000>,
+				<0xc3000000  0x9 0x80000000  0x9 0x80000000 0x0 0x40000000>;
 			msi-parent = <&plic>;
 			interrupts = <57>;
 			interrupt-controller;
@@ -1252,10 +1255,11 @@
 				 <&rstgen RSTN_U1_PLDA_PCIE_APB>;
 			reset-names = "rst_mst0", "rst_slv0", "rst_slv",
 				      "rst_brg", "rst_core", "rst_apb";
-			clocks = <&clkgen JH7110_PCIE1_CLK_TL>,
+			clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
+				 <&clkgen JH7110_PCIE1_CLK_TL>,
 				 <&clkgen JH7110_PCIE1_CLK_AXI_MST0>,
 				 <&clkgen JH7110_PCIE1_CLK_APB>;
-			clock-names =  "tl", "axi_mst0", "apb";
+			clock-names = "noc", "tl", "axi_mst0", "apb";
 			status = "disabled";
 		};
 
diff --git a/arch/riscv/dts/starfive_evb.dts b/arch/riscv/dts/starfive_evb.dts
index 47152ff829..dcccb48a39 100644
--- a/arch/riscv/dts/starfive_evb.dts
+++ b/arch/riscv/dts/starfive_evb.dts
@@ -163,6 +163,86 @@
 		};
 	};
 
+	pcie0_perst_default: pcie0_perst_default {
+		perst-pins {
+			pinmux = <GPIOMUX(26, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
+			drive-strength = <2>;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+
+	pcie0_perst_active: pcie0_perst_active {
+		perst-pins {
+			pinmux = <GPIOMUX(26, GPOUT_LOW, GPOEN_ENABLE, GPI_NONE)>;
+			drive-strength = <2>;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+
+	pcie0_power_default: pcie0_power_default {
+		power-pins {
+			pinmux = <GPIOMUX(32, GPOUT_LOW, GPOEN_ENABLE, GPI_NONE)>;
+			drive-strength = <2>;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+
+	pcie0_power_active: pcie0_power_active {
+		power-pins {
+			pinmux = <GPIOMUX(32, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
+			drive-strength = <2>;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+
+	pcie1_perst_default: pcie1_perst_default {
+		perst-pins {
+			pinmux = <GPIOMUX(28, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
+			drive-strength = <2>;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+
+	pcie1_perst_active: pcie1_perst_active {
+		perst-pins {
+			pinmux = <GPIOMUX(28, GPOUT_LOW, GPOEN_ENABLE, GPI_NONE)>;
+			drive-strength = <2>;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+
+	pcie1_power_default: pcie1_power_default {
+		power-pins {
+			pinmux = <GPIOMUX(21, GPOUT_LOW, GPOEN_ENABLE, GPI_NONE)>;
+			drive-strength = <2>;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+
+	pcie1_power_active: pcie1_power_active {
+		power-pins {
+			pinmux = <GPIOMUX(21, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
+			drive-strength = <2>;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+
 };
 
 &sdio0 {
@@ -224,6 +304,24 @@
 	pinctrl-0 = <&usb_pins>;
 };
 
+&pcie0 {
+	pinctrl-names = "perst-default", "perst-active", "power-default", "power-active";
+	pinctrl-0 = <&pcie0_perst_default>;
+	pinctrl-1 = <&pcie0_perst_active>;
+	pinctrl-2 = <&pcie0_power_default>;
+	pinctrl-3 = <&pcie0_power_active>;
+	status = "disabled";
+};
+
+&pcie1 {
+	pinctrl-names = "perst-default", "perst-active", "power-default", "power-active";
+	pinctrl-0 = <&pcie1_perst_default>;
+	pinctrl-1 = <&pcie1_perst_active>;
+	pinctrl-2 = <&pcie1_power_default>;
+	pinctrl-3 = <&pcie1_power_active>;
+	status = "okay";
+};
+
 &timer {
 	status = "disabled";
 };