diff options
| author | York Sun <york.sun@nxp.com> | 2016-04-04 21:41:26 +0300 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-04-06 20:26:46 +0300 |
| commit | 3c1d218a1d3048fb576677c47eab43049d0b7778 (patch) | |
| tree | fac5c6482522cef5563f368ee2777f4ed274759e /board/freescale/ls2080ardb/ls2080ardb.c | |
| parent | 2a5558399828e24fce9e948288a88cd28887875e (diff) | |
| download | u-boot-3c1d218a1d3048fb576677c47eab43049d0b7778.tar.xz | |
armv8: LS2080A: Consolidate LS2080A and LS2085A
LS2080A is the primary SoC, and LS2085A is a personality with AIOP
and DPAA DDR. The RDB and QDS boards support both personality. By
detecting the SVR at runtime, a single image per board can support
both SoCs. It gives users flexibility to swtich SoC without the need
to reprogram the board.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Diffstat (limited to 'board/freescale/ls2080ardb/ls2080ardb.c')
| -rw-r--r-- | board/freescale/ls2080ardb/ls2080ardb.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 8201048193..fb39af6445 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -207,7 +207,7 @@ void detail_board_ddr_info(void) print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); print_ddr_info(0); #ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (gd->bd->bi_dram[2].size) { + if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { puts("\nDP-DDR "); print_size(gd->bd->bi_dram[2].size, ""); print_ddr_info(CONFIG_DP_DDR_CTRL); |