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| author | Jagannadha Sutradharudu Teki <jagannadha.sutradharudu-teki@xilinx.com> | 2013-09-20 17:09:47 +0400 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2013-11-06 12:15:12 +0400 |
| commit | ec4b73f09c384007b274b38052149025e080b138 (patch) | |
| tree | 873b53a50014c59368f2c438917bec1a317212c4 /board/xaeniax | |
| parent | e5a9a4076f1fb9fb9ce53c2aec32422073bbc66a (diff) | |
| download | u-boot-ec4b73f09c384007b274b38052149025e080b138.tar.xz | |
fpga: zynqpl: Add dcache flush support
Buffers must be cache and dma aligned.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'board/xaeniax')
0 files changed, 0 insertions, 0 deletions