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| author | Simon Glass <sjg@chromium.org> | 2020-07-10 03:43:17 +0300 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2020-07-17 09:32:24 +0300 |
| commit | 0990c894cc2e8e94a2b049e4c83d484d0b3afd9c (patch) | |
| tree | e797cbeef5ba4fb68a87501773d48a8fba228351 /doc | |
| parent | ef5f5f6ca691ac0b08dfae45f8723668a9fc46b6 (diff) | |
| download | u-boot-0990c894cc2e8e94a2b049e4c83d484d0b3afd9c.tar.xz | |
x86: fsp: Support a warning message when DRAM init is slow
With DDR4, Intel SOCs take quite a long time to init their memory. During
this time, if the user is watching, it looks like SPL has hung. Add a
message in this case.
This works by adding a return code to fspm_update_config() that indicates
whether MRC data was found and a new property to the device tree.
Also add one more debug message while starting.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt b/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt index 647a0862d4..5311938f43 100644 --- a/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt +++ b/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt @@ -17,6 +17,10 @@ values of the FSP-M are used. [2] https://github.com/IntelFsp/FSP/tree/master/ApolloLakeFspBinPkg/Docs Optional properties: +- fspm,training-delay: Time taken to train DDR memory if there is no cached MRC + data, in seconds. This is used to show a message if possible. For Chromebook + Coral this is typically 21 seconds. For an APL board with 1GB of RAM, it may + be only 6 seconds. - fspm,serial-debug-port-address: Debug Serial Port Base address - fspm,serial-debug-port-type: Debug Serial Port Type 0: NONE |