diff options
| author | Kever Yang <kever.yang@rock-chips.com> | 2019-04-02 15:41:22 +0300 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2019-05-08 12:34:12 +0300 |
| commit | e4d0d61275ac1b14375be8f62585398e05b19f3f (patch) | |
| tree | 7e245f4fe36ba779ea19b27e18f92d9ccffa0814 /drivers/clk/rockchip/clk_rk322x.c | |
| parent | a0a0d04f3218507aaa29b4fdd45f37d819fb0a32 (diff) | |
| download | u-boot-e4d0d61275ac1b14375be8f62585398e05b19f3f.tar.xz | |
rockchip: rk322x: add CLK_EMMC_SAMPLE clock support
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'drivers/clk/rockchip/clk_rk322x.c')
| -rw-r--r-- | drivers/clk/rockchip/clk_rk322x.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index 48ed14b2af..4b599fbb24 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -217,6 +217,7 @@ static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate, switch (periph) { case HCLK_EMMC: case SCLK_EMMC: + case SCLK_EMMC_SAMPLE: con = readl(&cru->cru_clksel_con[11]); mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; con = readl(&cru->cru_clksel_con[12]); @@ -293,6 +294,7 @@ static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate, switch (periph) { case HCLK_EMMC: case SCLK_EMMC: + case SCLK_EMMC_SAMPLE: rk_clrsetreg(&cru->cru_clksel_con[11], EMMC_PLL_MASK, mux << EMMC_PLL_SHIFT); |