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| author | Tom Rini <trini@konsulko.com> | 2022-07-23 20:05:12 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-08-04 23:18:48 +0300 |
| commit | 78475d2572615471d3c047e61481a68859d0dd7f (patch) | |
| tree | d0de486d8215feedc0eba48c2e2b4428bd66d284 /drivers/ddr | |
| parent | 7da6a9e7df2f31f35391925042f58b19c7b7d9e4 (diff) | |
| download | u-boot-78475d2572615471d3c047e61481a68859d0dd7f.tar.xz | |
Convert CONFIG_SYS_FSL_DDR_INTLV_256B to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_FSL_DDR_INTLV_256B
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'drivers/ddr')
| -rw-r--r-- | drivers/ddr/fsl/Kconfig | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index d93ed8d2fe..22400a9b8b 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -182,6 +182,13 @@ config SYS_DDR_RAW_TIMING timing parameters are extracted from datasheet and hard-coded into header files or board specific files. +config SYS_FSL_DDR_INTLV_256B + bool "Enforce 256-byte interleave" + help + DDR controller interleaving on 256-byte. This is a special + interleaving mode, handled by Dickens for Freescale layerscape SoCs + with ARM core. + endif menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)" |