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| author | Christian Gmeiner <christian.gmeiner@gmail.com> | 2020-10-06 17:08:35 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-10-14 18:16:34 +0300 |
| commit | c90778ad70e2cf0844f0b10f8aad5d8cac11177a (patch) | |
| tree | c4b76f324b20a9c75f690dc2094d1937e540e340 /drivers/net/e1000.h | |
| parent | b9cca2c57a7f3f51dc044030a2f1665e517edb51 (diff) | |
| download | u-boot-c90778ad70e2cf0844f0b10f8aad5d8cac11177a.tar.xz | |
net: e1000: add defaults for i210 TX/RX PBSIZE
Set the defaults on probe for the packet buffer size registers
for the i210.
The TX/RX PBSIZE register of the i210 resets to its default value
only at power-on - see Intel Ethernet Controller I210 Datasheet rev 3.5
chapter 8.3 'Internal Packet Buffer Size Registers'.
If something (another driver, another OS, etc.) modifies this register
from its default value, the e1000 driver doesn't function correctly. It
detects a hang of the transmitter and continuously resets the adapter.
Here we set this value to its default when resetting the i210 to
resolve this issue.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Diffstat (limited to 'drivers/net/e1000.h')
| -rw-r--r-- | drivers/net/e1000.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h index 19ed4777d9..072851ba31 100644 --- a/drivers/net/e1000.h +++ b/drivers/net/e1000.h @@ -735,6 +735,7 @@ struct e1000_ffvt_entry { #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */ #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ +#define E1000_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */ #define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */ #define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */ #define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */ @@ -745,6 +746,7 @@ struct e1000_ffvt_entry { #define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */ #define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */ #define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */ +#define E1000_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */ #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ #define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */ @@ -2589,4 +2591,8 @@ struct e1000_hw { #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ + +#define I210_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */ +#define I210_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */ + #endif /* _E1000_HW_H_ */ |