net: mscc: refactor mscc_miim

Because all MSCC SoC use the same MDIO bus, put the implementation in
one common file(mscc_miim) and make all the other MSCC network drivers to
use these functions.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

1 files changed, 3 insertions, 101 deletions

diff --git a/drivers/net/mscc_eswitch/ocelot_switch.c b/drivers/net/mscc_eswitch/ocelot_switch.c
index 5c7e6961be..0ba84ab78a 100644
--- a/drivers/net/mscc_eswitch/ocelot_switch.c
+++ b/drivers/net/mscc_eswitch/ocelot_switch.c
@@ -17,6 +17,7 @@
 
 #include "mscc_xfer.h"
 #include "mscc_mac_table.h"
+#include "mscc_miim.h"
 
 #define PHY_CFG				0x0
 #define PHY_CFG_ENA				0xF
@@ -25,20 +26,6 @@
 #define PHY_STAT			0x4
 #define PHY_STAT_SUPERVISOR_COMPLETE		BIT(0)
 
-#define GCB_MIIM_MII_STATUS		0x0
-#define		GCB_MIIM_STAT_BUSY		BIT(3)
-#define GCB_MIIM_MII_CMD		0x8
-#define		GCB_MIIM_MII_CMD_SCAN		BIT(0)
-#define		GCB_MIIM_MII_CMD_OPR_WRITE	BIT(1)
-#define		GCB_MIIM_MII_CMD_OPR_READ	BIT(2)
-#define		GCB_MIIM_MII_CMD_SINGLE_SCAN	BIT(3)
-#define		GCB_MIIM_MII_CMD_WRDATA(x)	((x) << 4)
-#define		GCB_MIIM_MII_CMD_REGAD(x)	((x) << 20)
-#define		GCB_MIIM_MII_CMD_PHYAD(x)	((x) << 25)
-#define		GCB_MIIM_MII_CMD_VLD		BIT(31)
-#define GCB_MIIM_DATA			0xC
-#define		GCB_MIIM_DATA_ERROR		(0x3 << 16)
-
 #define ANA_PORT_VLAN_CFG(x)		(0x7000 + 0x100 * (x))
 #define		ANA_PORT_VLAN_CFG_AWARE_ENA	BIT(20)
 #define		ANA_PORT_VLAN_CFG_POP_CNT(x)	((x) << 18)
@@ -173,13 +160,6 @@ struct ocelot_private {
 	struct ocelot_phy_port_t ports[MAX_PORT];
 };
 
-struct mscc_miim_dev {
-	void __iomem *regs;
-	phys_addr_t miim_base;
-	unsigned long miim_size;
-	struct mii_dev *bus;
-};
-
 static struct mscc_miim_dev miim[OCELOT_MIIM_BUS_COUNT];
 static int miim_count = -1;
 
@@ -209,85 +189,6 @@ static void mscc_phy_reset(void)
 	}
 }
 
-static int mscc_miim_wait_ready(struct mscc_miim_dev *miim)
-{
-	return wait_for_bit_le32(miim->regs + GCB_MIIM_MII_STATUS,
-				 GCB_MIIM_STAT_BUSY, false, 250, false);
-}
-
-static int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg)
-{
-	struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
-	u32 val;
-	int ret;
-
-	ret = mscc_miim_wait_ready(miim);
-	if (ret)
-		goto out;
-
-	writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) |
-	       GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_OPR_READ,
-	       miim->regs + GCB_MIIM_MII_CMD);
-
-	ret = mscc_miim_wait_ready(miim);
-	if (ret)
-		goto out;
-
-	val = readl(miim->regs + GCB_MIIM_DATA);
-	if (val & GCB_MIIM_DATA_ERROR) {
-		ret = -EIO;
-		goto out;
-	}
-
-	ret = val & 0xFFFF;
- out:
-	return ret;
-}
-
-static int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg,
-			   u16 val)
-{
-	struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
-	int ret;
-
-	ret = mscc_miim_wait_ready(miim);
-	if (ret < 0)
-		goto out;
-
-	writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) |
-	       GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_WRDATA(val) |
-	       GCB_MIIM_MII_CMD_OPR_WRITE, miim->regs + GCB_MIIM_MII_CMD);
- out:
-	return ret;
-}
-
-static struct mii_dev *ocelot_mdiobus_init(phys_addr_t miim_base,
-					   unsigned long miim_size)
-{
-	struct mii_dev *bus;
-
-	bus = mdio_alloc();
-
-	if (!bus)
-		return NULL;
-
-	++miim_count;
-	sprintf(bus->name, "miim-bus%d", miim_count);
-
-	miim[miim_count].regs = ioremap(miim_base, miim_size);
-	miim[miim_count].miim_base = miim_base;
-	miim[miim_count].miim_size = miim_size;
-	bus->priv = &miim[miim_count];
-	bus->read = mscc_miim_read;
-	bus->write = mscc_miim_write;
-
-	if (mdio_register(bus))
-		return NULL;
-
-	miim[miim_count].bus = bus;
-	return bus;
-}
-
 __weak void mscc_switch_reset(void)
 {
 }
@@ -682,7 +583,8 @@ static int ocelot_probe(struct udevice *dev)
 		/* If the bus is new then create a new bus */
 		if (!get_mdiobus(addr_base, addr_size))
 			priv->bus[miim_count] =
-				ocelot_mdiobus_init(addr_base, addr_size);
+				mscc_mdiobus_init(miim, &miim_count, addr_base,
+						  addr_size);
 
 		/* Connect mdio bus with the port */
 		bus = get_mdiobus(addr_base, addr_size);