diff options
| author | Simon Glass <sjg@chromium.org> | 2020-05-10 20:40:10 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-05-19 04:19:23 +0300 |
| commit | 07e1114671c8b13d1bb90548a3c5ea31c49415d1 (patch) | |
| tree | d64c8a76ebfe729975a5b5a9e0b9f56bfdec01fb /drivers/net/smc91111.c | |
| parent | 1af3c7f422f627a544fec13e436d1a7975e39e73 (diff) | |
| download | u-boot-07e1114671c8b13d1bb90548a3c5ea31c49415d1.tar.xz | |
Fix some checkpatch warnings in calls to udelay()
Fix up some incorrect code style in calls to functions in the linux/time.h
header, mostly udelay().
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/net/smc91111.c')
| -rw-r--r-- | drivers/net/smc91111.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/drivers/net/smc91111.c b/drivers/net/smc91111.c index 5754c3106c..52bbf05a1e 100644 --- a/drivers/net/smc91111.c +++ b/drivers/net/smc91111.c @@ -266,7 +266,7 @@ static inline void smc_wait_mmu_release_complete (struct eth_device *dev) /* assume bank 2 selected */ while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { - udelay (1); /* Wait until not busy */ + udelay(1); /* Wait until not busy */ if (++count > 200) break; } @@ -318,7 +318,7 @@ static void smc_reset (struct eth_device *dev) SMC_SELECT_BANK (dev, 0); /* this should pause enough for the chip to be happy */ - udelay (10); + udelay(10); /* Disable transmit and receive functionality */ SMC_outw (dev, RCR_CLEAR, RCR_REG); @@ -333,7 +333,7 @@ static void smc_reset (struct eth_device *dev) smc_wait_mmu_release_complete (dev); SMC_outw (dev, MC_RESET, MMU_CMD_REG); while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) - udelay (1); /* Wait until not busy */ + udelay(1); /* Wait until not busy */ /* Note: It doesn't seem that waiting for the MMU busy is needed here, but this is a place where future chipsets _COULD_ break. Be wary @@ -564,7 +564,7 @@ again: /* wait for MMU getting ready (low) */ while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { - udelay (10); + udelay(10); } PRINTK2 ("MMU ready\n"); @@ -583,7 +583,7 @@ again: /* wait for MMU getting ready (low) */ while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { - udelay (10); + udelay(10); } PRINTK2 ("MMU ready\n"); @@ -957,19 +957,19 @@ static word smc_read_phy_register (struct eth_device *dev, byte phyreg) for (i = 0; i < sizeof bits; ++i) { /* Clock Low - output data */ SMC_outw (dev, mii_reg | bits[i], MII_REG); - udelay (SMC_PHY_CLOCK_DELAY); + udelay(SMC_PHY_CLOCK_DELAY); /* Clock Hi - input data */ SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG); - udelay (SMC_PHY_CLOCK_DELAY); + udelay(SMC_PHY_CLOCK_DELAY); bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI; } /* Return to idle state */ /* Set clock to low, data to low, and output tristated */ SMC_outw (dev, mii_reg, MII_REG); - udelay (SMC_PHY_CLOCK_DELAY); + udelay(SMC_PHY_CLOCK_DELAY); /* Restore original bank select */ SMC_SELECT_BANK (dev, oldBank); @@ -1078,19 +1078,19 @@ static void smc_write_phy_register (struct eth_device *dev, byte phyreg, for (i = 0; i < sizeof bits; ++i) { /* Clock Low - output data */ SMC_outw (dev, mii_reg | bits[i], MII_REG); - udelay (SMC_PHY_CLOCK_DELAY); + udelay(SMC_PHY_CLOCK_DELAY); /* Clock Hi - input data */ SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG); - udelay (SMC_PHY_CLOCK_DELAY); + udelay(SMC_PHY_CLOCK_DELAY); bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI; } /* Return to idle state */ /* Set clock to low, data to low, and output tristated */ SMC_outw (dev, mii_reg, MII_REG); - udelay (SMC_PHY_CLOCK_DELAY); + udelay(SMC_PHY_CLOCK_DELAY); /* Restore original bank select */ SMC_SELECT_BANK (dev, oldBank); |