diff options
author | Tom Rini <trini@konsulko.com> | 2022-05-25 06:29:00 +0300 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2022-05-25 06:29:00 +0300 |
commit | 7e0edcadb09d55d5319fdc862041fd1b874476f5 (patch) | |
tree | 3c5b591fea0c39989c580df0cdc78c6731a317eb /drivers | |
parent | 1b04a961c6bcb9768f517198890cac680ee532e8 (diff) | |
parent | 7495051219b64ec0e8fac8930586dc10666530da (diff) | |
download | u-boot-7e0edcadb09d55d5319fdc862041fd1b874476f5.tar.xz |
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
The bulk of it is (finally!) some DT sync from the kernel. We refrained
from syncing one incompatible change, as this would spoil booting Linux
kernels before v5.13 with U-Boot's DT (via UEFI, for instance).
I test booted Linux v5.18 and v5.4 with that new DT on some boards, and
the headless peripherals (MMC, USB, Ethernet) seemed to work.
The rest are fixes:
- silencing missing clock warnings due to the new pinctrl driver
- fixing "UART0 on PortF", allowing UART access through the SD card pins
- add an F1C100s clock driver, to enable MMC support (SPI comes later)
- some cleanups for CONS_INDEX_n in Kconfig
Tested on BananaPi-M1, Pine64-LTS, Pine-H64, X96-Mate (H616) and
OrangePi-Zero.
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/clk/sunxi/Kconfig | 7 | ||||
-rw-r--r-- | drivers/clk/sunxi/Makefile | 1 | ||||
-rw-r--r-- | drivers/clk/sunxi/clk_a10.c | 2 | ||||
-rw-r--r-- | drivers/clk/sunxi/clk_a10s.c | 2 | ||||
-rw-r--r-- | drivers/clk/sunxi/clk_a23.c | 2 | ||||
-rw-r--r-- | drivers/clk/sunxi/clk_a31.c | 2 | ||||
-rw-r--r-- | drivers/clk/sunxi/clk_a64.c | 4 | ||||
-rw-r--r-- | drivers/clk/sunxi/clk_a80.c | 2 | ||||
-rw-r--r-- | drivers/clk/sunxi/clk_a83t.c | 2 | ||||
-rw-r--r-- | drivers/clk/sunxi/clk_f1c100s.c | 74 | ||||
-rw-r--r-- | drivers/clk/sunxi/clk_h3.c | 4 | ||||
-rw-r--r-- | drivers/clk/sunxi/clk_h6.c | 4 | ||||
-rw-r--r-- | drivers/clk/sunxi/clk_h616.c | 4 | ||||
-rw-r--r-- | drivers/clk/sunxi/clk_h6_r.c | 6 | ||||
-rw-r--r-- | drivers/clk/sunxi/clk_r40.c | 2 | ||||
-rw-r--r-- | drivers/clk/sunxi/clk_sunxi.c | 3 | ||||
-rw-r--r-- | drivers/clk/sunxi/clk_v3s.c | 2 | ||||
-rw-r--r-- | drivers/mmc/Kconfig | 2 | ||||
-rw-r--r-- | drivers/serial/Kconfig | 26 |
19 files changed, 122 insertions, 29 deletions
diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index f19908113e..bf11fad6ee 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -10,6 +10,13 @@ config CLK_SUNXI if CLK_SUNXI +config CLK_SUNIV_F1C100S + bool "Clock driver for Allwinner F1C100s" + default MACH_SUNIV + help + This enables common clock driver support for platforms based + on Allwinner F1C100s SoC. + config CLK_SUN4I_A10 bool "Clock driver for Allwinner A10/A20" default MACH_SUN4I || MACH_SUN7I diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index 48a48a2f00..895da02ebe 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o obj-$(CONFIG_CLK_SUNXI) += clk_sun6i_rtc.o +obj-$(CONFIG_CLK_SUNIV_F1C100S) += clk_f1c100s.o obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c index 90b929d3d3..db92848aaf 100644 --- a/drivers/clk/sunxi/clk_a10.c +++ b/drivers/clk/sunxi/clk_a10.c @@ -31,6 +31,8 @@ static struct ccu_clk_gate a10_gates[] = { [CLK_AHB_GMAC] = GATE(0x064, BIT(17)), + [CLK_APB0_PIO] = GATE(0x068, BIT(5)), + [CLK_APB1_I2C0] = GATE(0x06c, BIT(0)), [CLK_APB1_I2C1] = GATE(0x06c, BIT(1)), [CLK_APB1_I2C2] = GATE(0x06c, BIT(2)), diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c index addf4f4d5c..0c6564ef3b 100644 --- a/drivers/clk/sunxi/clk_a10s.c +++ b/drivers/clk/sunxi/clk_a10s.c @@ -25,6 +25,8 @@ static struct ccu_clk_gate a10s_gates[] = { [CLK_AHB_SPI1] = GATE(0x060, BIT(21)), [CLK_AHB_SPI2] = GATE(0x060, BIT(22)), + [CLK_APB0_PIO] = GATE(0x068, BIT(5)), + [CLK_APB1_I2C0] = GATE(0x06c, BIT(0)), [CLK_APB1_I2C1] = GATE(0x06c, BIT(1)), [CLK_APB1_I2C2] = GATE(0x06c, BIT(2)), diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c index c45d2c3529..0280fb51e2 100644 --- a/drivers/clk/sunxi/clk_a23.c +++ b/drivers/clk/sunxi/clk_a23.c @@ -23,6 +23,8 @@ static struct ccu_clk_gate a23_gates[] = { [CLK_BUS_EHCI] = GATE(0x060, BIT(26)), [CLK_BUS_OHCI] = GATE(0x060, BIT(29)), + [CLK_BUS_PIO] = GATE(0x068, BIT(5)), + [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)), diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c index 251fc3b705..26d25f3240 100644 --- a/drivers/clk/sunxi/clk_a31.c +++ b/drivers/clk/sunxi/clk_a31.c @@ -30,6 +30,8 @@ static struct ccu_clk_gate a31_gates[] = { [CLK_AHB1_OHCI1] = GATE(0x060, BIT(30)), [CLK_AHB1_OHCI2] = GATE(0x060, BIT(31)), + [CLK_APB1_PIO] = GATE(0x068, BIT(5)), + [CLK_APB2_I2C0] = GATE(0x06c, BIT(0)), [CLK_APB2_I2C1] = GATE(0x06c, BIT(1)), [CLK_APB2_I2C2] = GATE(0x06c, BIT(2)), diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c index 1004a79503..cbb9168edb 100644 --- a/drivers/clk/sunxi/clk_a64.c +++ b/drivers/clk/sunxi/clk_a64.c @@ -14,6 +14,8 @@ #include <linux/bitops.h> static const struct ccu_clk_gate a64_gates[] = { + [CLK_PLL_PERIPH0] = GATE(0x028, BIT(31)), + [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), @@ -26,6 +28,8 @@ static const struct ccu_clk_gate a64_gates[] = { [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)), [CLK_BUS_OHCI1] = GATE(0x060, BIT(29)), + [CLK_BUS_PIO] = GATE(0x068, BIT(5)), + [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)), diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c index 8a0834d83a..1ee1f99a8f 100644 --- a/drivers/clk/sunxi/clk_a80.c +++ b/drivers/clk/sunxi/clk_a80.c @@ -25,6 +25,8 @@ static const struct ccu_clk_gate a80_gates[] = { [CLK_BUS_SPI2] = GATE(0x580, BIT(22)), [CLK_BUS_SPI3] = GATE(0x580, BIT(23)), + [CLK_BUS_PIO] = GATE(0x590, BIT(5)), + [CLK_BUS_I2C0] = GATE(0x594, BIT(0)), [CLK_BUS_I2C1] = GATE(0x594, BIT(1)), [CLK_BUS_I2C2] = GATE(0x594, BIT(2)), diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c index 8c6043f51e..4b57434cfa 100644 --- a/drivers/clk/sunxi/clk_a83t.c +++ b/drivers/clk/sunxi/clk_a83t.c @@ -25,6 +25,8 @@ static struct ccu_clk_gate a83t_gates[] = { [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)), [CLK_BUS_OHCI0] = GATE(0x060, BIT(29)), + [CLK_BUS_PIO] = GATE(0x068, BIT(5)), + [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)), diff --git a/drivers/clk/sunxi/clk_f1c100s.c b/drivers/clk/sunxi/clk_f1c100s.c new file mode 100644 index 0000000000..72cf8a6e5c --- /dev/null +++ b/drivers/clk/sunxi/clk_f1c100s.c @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: (GPL-2.0+) +/* + * Copyright (C) 2019 George Hilliard <thirtythreeforty@gmail.com>. + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <clk/sunxi.h> +#include <dt-bindings/clock/suniv-ccu-f1c100s.h> +#include <dt-bindings/reset/suniv-ccu-f1c100s.h> + +static struct ccu_clk_gate f1c100s_gates[] = { + [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), + [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), + [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), + [CLK_BUS_SPI1] = GATE(0x060, BIT(21)), + [CLK_BUS_OTG] = GATE(0x060, BIT(24)), + + [CLK_BUS_I2C0] = GATE(0x068, BIT(16)), + [CLK_BUS_I2C1] = GATE(0x068, BIT(17)), + [CLK_BUS_I2C2] = GATE(0x068, BIT(18)), + [CLK_BUS_PIO] = GATE(0x068, BIT(19)), + + [CLK_BUS_UART0] = GATE(0x06c, BIT(20)), + [CLK_BUS_UART1] = GATE(0x06c, BIT(21)), + [CLK_BUS_UART2] = GATE(0x06c, BIT(22)), + + [CLK_USB_PHY0] = GATE(0x0cc, BIT(1)), +}; + +static struct ccu_reset f1c100s_resets[] = { + [RST_USB_PHY0] = RESET(0x0cc, BIT(0)), + + [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), + [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), + [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)), + [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)), + [RST_BUS_OTG] = RESET(0x2c0, BIT(24)), + + [RST_BUS_I2C0] = RESET(0x2d0, BIT(16)), + [RST_BUS_I2C1] = RESET(0x2d0, BIT(17)), + [RST_BUS_I2C2] = RESET(0x2d0, BIT(18)), + [RST_BUS_UART0] = RESET(0x2d0, BIT(20)), + [RST_BUS_UART1] = RESET(0x2d0, BIT(21)), + [RST_BUS_UART2] = RESET(0x2d0, BIT(22)), +}; + +static const struct ccu_desc f1c100s_ccu_desc = { + .gates = f1c100s_gates, + .resets = f1c100s_resets, +}; + +static int f1c100s_clk_bind(struct udevice *dev) +{ + return sunxi_reset_bind(dev, ARRAY_SIZE(f1c100s_resets)); +} + +static const struct udevice_id f1c100s_clk_ids[] = { + { .compatible = "allwinner,suniv-f1c100s-ccu", + .data = (ulong)&f1c100s_ccu_desc }, + { } +}; + +U_BOOT_DRIVER(clk_suniv_f1c100s) = { + .name = "suniv_f1c100s_ccu", + .id = UCLASS_CLK, + .of_match = f1c100s_clk_ids, + .priv_auto = sizeof(struct ccu_priv), + .ops = &sunxi_clk_ops, + .probe = sunxi_clk_probe, + .bind = f1c100s_clk_bind, +}; diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c index 59afba53ee..08a830bd18 100644 --- a/drivers/clk/sunxi/clk_h3.c +++ b/drivers/clk/sunxi/clk_h3.c @@ -14,6 +14,8 @@ #include <linux/bitops.h> static struct ccu_clk_gate h3_gates[] = { + [CLK_PLL_PERIPH0] = GATE(0x028, BIT(31)), + [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), @@ -30,6 +32,8 @@ static struct ccu_clk_gate h3_gates[] = { [CLK_BUS_OHCI2] = GATE(0x060, BIT(30)), [CLK_BUS_OHCI3] = GATE(0x060, BIT(31)), + [CLK_BUS_PIO] = GATE(0x068, BIT(5)), + [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)), diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c index 4a53788352..b320234293 100644 --- a/drivers/clk/sunxi/clk_h6.c +++ b/drivers/clk/sunxi/clk_h6.c @@ -14,6 +14,10 @@ #include <linux/bitops.h> static struct ccu_clk_gate h6_gates[] = { + [CLK_PLL_PERIPH0] = GATE(0x020, BIT(31)), + + [CLK_APB1] = GATE_DUMMY, + [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)), [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)), [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)), diff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c index af97d3bb9f..80099727de 100644 --- a/drivers/clk/sunxi/clk_h616.c +++ b/drivers/clk/sunxi/clk_h616.c @@ -13,6 +13,10 @@ #include <linux/bitops.h> static struct ccu_clk_gate h616_gates[] = { + [CLK_PLL_PERIPH0] = GATE(0x020, BIT(31) | BIT(27)), + + [CLK_APB1] = GATE_DUMMY, + [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)), [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)), [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)), diff --git a/drivers/clk/sunxi/clk_h6_r.c b/drivers/clk/sunxi/clk_h6_r.c index b9e527e16a..c592886a25 100644 --- a/drivers/clk/sunxi/clk_h6_r.c +++ b/drivers/clk/sunxi/clk_h6_r.c @@ -11,6 +11,8 @@ #include <linux/bitops.h> static struct ccu_clk_gate h6_r_gates[] = { + [CLK_R_APB1] = GATE_DUMMY, + [CLK_R_APB1_TIMER] = GATE(0x11c, BIT(0)), [CLK_R_APB1_TWD] = GATE(0x12c, BIT(0)), [CLK_R_APB1_PWM] = GATE(0x13c, BIT(0)), @@ -50,8 +52,8 @@ static const struct udevice_id h6_r_clk_ids[] = { { } }; -U_BOOT_DRIVER(clk_sun6i_h6_r) = { - .name = "sun6i_h6_r_ccu", +U_BOOT_DRIVER(clk_sun50i_h6_r) = { + .name = "sun50i_h6_r_ccu", .id = UCLASS_CLK, .of_match = h6_r_clk_ids, .priv_auto = sizeof(struct ccu_priv), diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c index 4d5b69a976..45633a2a52 100644 --- a/drivers/clk/sunxi/clk_r40.c +++ b/drivers/clk/sunxi/clk_r40.c @@ -32,6 +32,8 @@ static struct ccu_clk_gate r40_gates[] = { [CLK_BUS_GMAC] = GATE(0x064, BIT(17)), + [CLK_BUS_PIO] = GATE(0x068, BIT(5)), + [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)), diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c index 9673b58a49..9a21367a5d 100644 --- a/drivers/clk/sunxi/clk_sunxi.c +++ b/drivers/clk/sunxi/clk_sunxi.c @@ -27,6 +27,9 @@ static int sunxi_set_gate(struct clk *clk, bool on) const struct ccu_clk_gate *gate = priv_to_gate(priv, clk->id); u32 reg; + if ((gate->flags & CCU_CLK_F_DUMMY_GATE)) + return 0; + if (!(gate->flags & CCU_CLK_F_IS_VALID)) { printf("%s: (CLK#%ld) unhandled\n", __func__, clk->id); return 0; diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c index cce5c658ca..67d215cbba 100644 --- a/drivers/clk/sunxi/clk_v3s.c +++ b/drivers/clk/sunxi/clk_v3s.c @@ -20,6 +20,8 @@ static struct ccu_clk_gate v3s_gates[] = { [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), [CLK_BUS_OTG] = GATE(0x060, BIT(24)), + [CLK_BUS_PIO] = GATE(0x068, BIT(5)), + [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index f04cc44e19..5e2921ce41 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -727,7 +727,7 @@ config ZYNQ_HISPD_BROKEN config MMC_SUNXI bool "Allwinner sunxi SD/MMC Host Controller support" - depends on ARCH_SUNXI && !UART0_PORT_F + depends on ARCH_SUNXI default y help This selects support for the SD/MMC Host Controller on diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index f6425a530e..45c284a408 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -84,36 +84,10 @@ config VPL_SERIAL_PRESENT This option enables the full UART in TPL, so if is it disabled, the full UART driver will be omitted, thus saving space. -# Logic to allow us to use the imply keyword to set what the default port -# should be. The default is otherwise 1. -config CONS_INDEX_0 - bool - -config CONS_INDEX_2 - bool - -config CONS_INDEX_3 - bool - -config CONS_INDEX_4 - bool - -config CONS_INDEX_5 - bool - -config CONS_INDEX_6 - bool - config CONS_INDEX int "UART used for console" depends on SPECIFY_CONSOLE_INDEX range 0 6 - default 0 if CONS_INDEX_0 - default 2 if CONS_INDEX_2 - default 3 if CONS_INDEX_3 - default 4 if CONS_INDEX_4 - default 5 if CONS_INDEX_5 - default 6 if CONS_INDEX_6 default 1 help Set this to match the UART number of the serial console. |