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| author | Ashish Kumar <Ashish.Kumar@nxp.com> | 2018-02-19 11:46:58 +0300 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2018-03-20 18:27:13 +0300 |
| commit | c1c597e8a8abfe16938ce8a1d792c703c1a6c79b (patch) | |
| tree | e3ac02306d379707bc89a25dc839b5ebee361272 /include/configs/ls1088aqds.h | |
| parent | 169d493bb7dd3fdcfb04d266e1492ddcf298b1df (diff) | |
| download | u-boot-c1c597e8a8abfe16938ce8a1d792c703c1a6c79b.tar.xz | |
armv8: ls1088aqds: Add IFC-NOR as boot source for LS1088
IFC-NOR and QSPI-NOR pins are multiplexed on SoC, so they cannot be
accessed simultaneously. IFC-NOR can be accessed along with SD-BOOT.
Ls1088aqds_sdcard_ifc_defconfig is default config for SD boot and
IFC-NOR to be used as flash. This allows writing to IFC-NOR flash.
QSPI and DSPI cannot be accessed in this defconfig.
IFC-NOR image is generated using ls1088aqds_defconfig.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'include/configs/ls1088aqds.h')
| -rw-r--r-- | include/configs/ls1088aqds.h | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index 5de364e08b..34f991caa5 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -27,7 +27,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 #else -#define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) #define CONFIG_ENV_SECT_SIZE 0x20000 #define CONFIG_ENV_SIZE 0x20000 @@ -41,6 +40,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 100000000 #else +#define CONFIG_QIXIS_I2C_ACCESS +#define CONFIG_SYS_I2C_EARLY_INIT #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() #endif @@ -89,13 +90,14 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TAVDS(0x6) | \ FTIM0_NOR_TEAHC(0x5)) #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ - FTIM1_NOR_TRAD_NOR(0x1a) |\ + FTIM1_NOR_TRAD_NOR(0x1a) | \ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ - FTIM2_NOR_TCH(0x4) | \ - FTIM2_NOR_TWPH(0x0E) | \ +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ + FTIM2_NOR_TCH(0x8) | \ + FTIM2_NOR_TWPH(0xe) | \ FTIM2_NOR_TWP(0x1c)) #define CONFIG_SYS_NOR_FTIM3 0x04000000 #define CONFIG_SYS_IFC_CCR 0x01000000 |