diff options
| -rw-r--r-- | drivers/reset/Kconfig | 16 | ||||
| -rw-r--r-- | drivers/reset/Makefile | 1 | ||||
| -rw-r--r-- | drivers/reset/reset-jh7110.c | 158 |
3 files changed, 175 insertions, 0 deletions
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index e4039d7474..73bbd30692 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -172,6 +172,22 @@ config RESET_SIFIVE different hw blocks like DDR, gemgxl. With this driver we leverage U-Boot's reset framework to reset these hardware blocks. +config RESET_JH7110 + bool "Reset driver for StarFive JH7110 SoC" + depends on DM_RESET && STARFIVE_JH7110 + default y + help + Support for reset controller on StarFive + JH7110 SoCs. + +config SPL_RESET_JH7110 + bool "SPL Reset driver for StarFive JH7110 SoC" + depends on SPL && STARFIVE_JH7110 + default y + help + Support for reset controller on StarFive + JH7110 SoCs in SPL. + config RESET_SYSCON bool "Enable generic syscon reset driver support" depends on DM_RESET diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 6c8b45ecba..6801268180 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -32,3 +32,4 @@ obj-$(CONFIG_RESET_SCMI) += reset-scmi.o obj-$(CONFIG_RESET_ZYNQMP) += reset-zynqmp.o obj-$(CONFIG_RESET_DRA7) += reset-dra7.o obj-$(CONFIG_RESET_AT91) += reset-at91.o +obj-$(CONFIG_$(SPL_TPL_)RESET_JH7110) += reset-jh7110.o diff --git a/drivers/reset/reset-jh7110.c b/drivers/reset/reset-jh7110.c new file mode 100644 index 0000000000..d6bdf6bb00 --- /dev/null +++ b/drivers/reset/reset-jh7110.c @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Yanhong Wang <yanhong.wang@starfivetech.com> + * + */ + +#include <common.h> +#include <dm.h> +#include <dm/ofnode.h> +#include <dt-bindings/reset/starfive,jh7110-crg.h> +#include <errno.h> +#include <linux/iopoll.h> +#include <reset-uclass.h> + +struct jh7110_reset_priv { + void __iomem *reg; + u32 assert; + u32 status; + u32 resets; +}; + +struct reset_info { + const char *compat; + const u32 nr_resets; + const u32 assert_offset; + const u32 status_offset; +}; + +static const struct reset_info jh7110_rst_info[] = { + { + .compat = "starfive,jh7110-syscrg", + .nr_resets = JH7110_SYSRST_END, + .assert_offset = 0x2F8, + .status_offset = 0x308, + }, + { + .compat = "starfive,jh7110-aoncrg", + .nr_resets = JH7110_AONRST_END, + .assert_offset = 0x38, + .status_offset = 0x3C, + }, + { + .compat = "starfive,jh7110-stgcrg", + .nr_resets = JH7110_STGRST_END, + .assert_offset = 0x74, + .status_offset = 0x78, + } +}; + +static const struct reset_info *jh7110_reset_get_cfg(const char *compat) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(jh7110_rst_info); i++) + if (!strcmp(compat, jh7110_rst_info[i].compat)) + return &jh7110_rst_info[i]; + + return NULL; +} + +static int jh7110_reset_trigger(struct jh7110_reset_priv *priv, + unsigned long id, bool assert) +{ + ulong group; + u32 mask, value, done = 0; + ulong addr; + + group = id / 32; + mask = BIT(id % 32); + + if (!assert) + done ^= mask; + + addr = (ulong)priv->reg + priv->assert + group * sizeof(u32); + value = readl((ulong *)addr); + + if (assert) + value |= mask; + else + value &= ~mask; + + writel(value, (ulong *)addr); + addr = (ulong)priv->reg + priv->status + group * sizeof(u32); + + return readl_poll_timeout((ulong *)addr, value, + (value & mask) == done, 1000); +} + +static int jh7110_reset_assert(struct reset_ctl *rst) +{ + struct jh7110_reset_priv *priv = dev_get_priv(rst->dev); + + jh7110_reset_trigger(priv, rst->id, true); + + return 0; +} + +static int jh7110_reset_deassert(struct reset_ctl *rst) +{ + struct jh7110_reset_priv *priv = dev_get_priv(rst->dev); + + jh7110_reset_trigger(priv, rst->id, false); + + return 0; +} + +static int jh7110_reset_free(struct reset_ctl *rst) +{ + return 0; +} + +static int jh7110_reset_request(struct reset_ctl *rst) +{ + struct jh7110_reset_priv *priv = dev_get_priv(rst->dev); + + if (rst->id >= priv->resets) + return -EINVAL; + + return 0; +} + +static int jh7110_reset_probe(struct udevice *dev) +{ + struct jh7110_reset_priv *priv = dev_get_priv(dev); + const struct reset_info *cfg; + const char *compat; + + compat = ofnode_get_property(dev_ofnode(dev), "compatible", NULL); + if (!compat) + return -EINVAL; + + cfg = jh7110_reset_get_cfg(compat); + if (!cfg) + return -EINVAL; + + priv->assert = cfg->assert_offset; + priv->status = cfg->status_offset; + priv->resets = cfg->nr_resets; + priv->reg = (void __iomem *)dev_read_addr_index(dev, 0); + + return 0; +} + +const struct reset_ops jh7110_reset_reset_ops = { + .rfree = jh7110_reset_free, + .request = jh7110_reset_request, + .rst_assert = jh7110_reset_assert, + .rst_deassert = jh7110_reset_deassert, +}; + +U_BOOT_DRIVER(jh7110_reset) = { + .name = "jh7110_reset", + .id = UCLASS_RESET, + .ops = &jh7110_reset_reset_ops, + .probe = jh7110_reset_probe, + .priv_auto = sizeof(struct jh7110_reset_priv), +}; |