diff options
Diffstat (limited to 'arch/arm/dts')
38 files changed, 741 insertions, 817 deletions
diff --git a/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts b/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts index 85ab9e9e29..6d1448e869 100644 --- a/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts +++ b/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts @@ -15,10 +15,10 @@ "xlnx,zynqmp"; chosen { stdout-path = "serial0:115200n8"; - xlnx,eeprom = &eeprom; }; aliases { ethernet0 = &gem3; + nvmem0 = &eeprom; serial0 = &uart0; }; }; diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index c35eb2344f..4dda753671 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -95,7 +95,7 @@ }; }; - amba: amba { + amba: axi { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/dts/zynq-syzygy-hub.dts b/arch/arm/dts/zynq-syzygy-hub.dts index 55f8e8a2da..cb878b0d0d 100644 --- a/arch/arm/dts/zynq-syzygy-hub.dts +++ b/arch/arm/dts/zynq-syzygy-hub.dts @@ -16,6 +16,7 @@ ethernet0 = &gem0; serial0 = &uart0; mmc0 = &sdhci0; + nvmem0 = &eeprom; i2c0 = &i2c1; }; @@ -27,7 +28,6 @@ chosen { bootargs = ""; stdout-path = "serial0:115200n8"; - xlnx,eeprom = &eeprom; }; usb_phy0: phy0 { diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index e45eba3d90..4474f4bfd7 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -68,6 +68,12 @@ ocm: sram@fffc0000 { compatible = "mmio-sram"; reg = <0xfffc0000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xfffc0000 0x10000>; + ocm-sram@0 { + reg = <0x0 0x10000>; + }; }; }; diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts index bdf0c2f956..7218ee3ad8 100644 --- a/arch/arm/dts/zynq-zc770-xm013.dts +++ b/arch/arm/dts/zynq-zc770-xm013.dts @@ -68,13 +68,12 @@ num-cs = <4>; is-decoded-cs = <0>; eeprom: eeprom@2 { - at25,byte-len = <8192>; - at25,addr-mode = <2>; - at25,page-size = <32>; - compatible = "atmel,at25"; reg = <2>; spi-max-frequency = <1000000>; + size = <8192>; + address-width = <16>; + pagesize = <32>; }; }; diff --git a/arch/arm/dts/zynqmp-a2197-revA.dts b/arch/arm/dts/zynqmp-a2197-revA.dts index 3153138542..89c3a281d0 100644 --- a/arch/arm/dts/zynqmp-a2197-revA.dts +++ b/arch/arm/dts/zynqmp-a2197-revA.dts @@ -18,13 +18,14 @@ aliases { i2c0 = &i2c0; + nvmem0 = &eeprom1; + nvmem1 = &eeprom0; serial0 = &uart0; }; chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; - xlnx,eeprom = <&eeprom1 &eeprom0 &eeprom0>; }; memory@0 { @@ -35,7 +36,6 @@ &uart0 { /* uart0 MIO38-39 */ status = "okay"; - u-boot,dm-pre-reloc; }; &i2c0 { diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 987792e5c5..b27b0aaf7c 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -2,7 +2,7 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> */ @@ -67,13 +67,6 @@ #clock-cells = <0>; clock-frequency = <27000000>; }; - - dp_aclk: dp_aclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-accuracy = <100>; - }; }; &zynqmp_firmware { diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index 8ec2e86653..bd0ba557e0 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -20,10 +20,10 @@ aliases { ethernet0 = &gem0; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; + nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; @@ -32,7 +32,6 @@ chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; - xlnx,eeprom = <&eeprom>; }; memory@0 { @@ -124,7 +123,6 @@ &uart0 { /* uart0 MIO38-39 */ status = "okay"; - u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts index f94b797d1a..ee530ba3e1 100644 --- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts @@ -19,9 +19,9 @@ aliases { ethernet0 = &gem0; - gpio0 = &gpio; i2c0 = &i2c0; mmc0 = &sdhci0; + nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; @@ -31,7 +31,6 @@ chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; - xlnx,eeprom = <&eeprom>; }; memory@0 { @@ -75,7 +74,6 @@ &uart0 { /* uart0 MIO38-39 */ status = "okay"; - u-boot,dm-pre-reloc; }; &gem0 { /* eth MDIO 76/77 */ diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts index 213149a3dc..86f2ccf4d9 100644 --- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts @@ -19,11 +19,11 @@ aliases { ethernet0 = &gem0; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; + nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; @@ -36,7 +36,6 @@ chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; - xlnx,eeprom = <&eeprom>; }; memory@0 { @@ -94,12 +93,10 @@ &uart0 { /* uart0 MIO38-39 */ status = "okay"; - u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ status = "okay"; - u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts index c458110e5a..e980fb07fc 100644 --- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts @@ -19,11 +19,11 @@ aliases { ethernet0 = &gem0; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; + nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; @@ -36,7 +36,6 @@ chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; - xlnx,eeprom = <&eeprom>; }; memory@0 { @@ -90,12 +89,10 @@ &uart0 { /* uart0 MIO38-39 */ status = "okay"; - u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ status = "okay"; - u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts index cee7ca1fa9..c8c5100672 100644 --- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts @@ -19,11 +19,11 @@ aliases { ethernet0 = &gem0; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; + nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; @@ -36,7 +36,6 @@ chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; - xlnx,eeprom = <&eeprom>; }; memory@0 { @@ -90,12 +89,10 @@ &uart0 { /* uart0 MIO38-39 */ status = "okay"; - u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ status = "okay"; - u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts index 1f5201ac88..d50b335e67 100644 --- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts @@ -20,11 +20,11 @@ aliases { ethernet0 = &gem0; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; + nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; @@ -36,8 +36,6 @@ chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; - xlnx,eeprom = <&eeprom>; - /* xlnx,fmc-eeprom = FIXME */ }; memory@0 { @@ -68,12 +66,10 @@ &uart0 { /* uart0 MIO38-39 */ status = "okay"; - u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ status = "okay"; - u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts index cad2d05721..59d5751e06 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts @@ -2,7 +2,7 @@ /* * dts file for KV260 revA Carrier Card * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020 - 2021, Xilinx, Inc. * * SD level shifter: * "A" – A01 board un-modified (NXP) @@ -20,354 +20,316 @@ /dts-v1/; /plugin/; -/{ +&{/} { compatible = "xlnx,zynqmp-sk-kv260-revA", "xlnx,zynqmp-sk-kv260-revY", "xlnx,zynqmp-sk-kv260-revZ", "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp"; +}; - fragment1 { - target = <&i2c1>; /* I2C_SCK C23/C24 - MIO from SOM */ - - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1_default>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; - - u14: ina260@40 { /* u14 */ - compatible = "ti,ina260"; - #io-channel-cells = <1>; - label = "ina260-u14"; - reg = <0x40>; - }; - /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ - }; +&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + + u14: ina260@40 { /* u14 */ + compatible = "ti,ina260"; + #io-channel-cells = <1>; + label = "ina260-u14"; + reg = <0x40>; }; + /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ +}; - fragment1a { - target = <&amba>; - __overlay__ { - ina260-u14 { - compatible = "iio-hwmon"; - io-channels = <&u14 0>, <&u14 1>, <&u14 2>; - }; - - si5332_0: si5332_0 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; - - si5332_1: si5332_1 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - si5332_2: si5332_2 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; - - si5332_3: si5332_3 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - - si5332_4: si5332_4 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - - si5332_5: si5332_5 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - }; - }; +&amba { + ina260-u14 { + compatible = "iio-hwmon"; + io-channels = <&u14 0>, <&u14 1>, <&u14 2>; }; + si5332_0: si5332_0 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + si5332_1: si5332_1 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + si5332_2: si5332_2 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + si5332_3: si5332_3 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + si5332_4: si5332_4 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + si5332_5: si5332_5 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; +}; + /* DP/USB 3.0 and SATA */ - fragment2 { - target = <&psgtr>; - __overlay__ { - status = "okay"; - /* pcie, usb3, sata */ - clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>; - clock-names = "ref0", "ref1", "ref2"; - }; +&psgtr { + status = "okay"; + /* pcie, usb3, sata */ + clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>; + clock-names = "ref0", "ref1", "ref2"; +}; + +&sata { + status = "okay"; + /* SATA OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + phy-names = "sata-phy"; + phys = <&psgtr 3 PHY_TYPE_SATA 1 2>; +}; + +&zynqmp_dpsub { + status = "disabled"; + phy-names = "dp-phy0", "dp-phy1"; + phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; +}; + +&zynqmp_dpdma { + status = "okay"; +}; + +&usb0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; + usbhub: usb5744 { /* u43 */ + compatible = "microchip,usb5744"; + reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>; }; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + phy-names = "usb3-phy"; + phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; + maximum-speed = "super-speed"; +}; + +&sdhci1 { /* on CC with tuned parameters */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci1_default>; + /* + * SD 3.0 requires level shifter and this property + * should be removed if the board has level shifter and + * need to work in UHS mode + */ + no-1-8-v; + disable-wp; + xlnx,mio-bank = <1>; +}; - fragment3 { - target = <&sata>; - __overlay__ { - status = "okay"; - /* SATA OOB timing settings */ - ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; - ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; - ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; - ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; - ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; - ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; - phy-names = "sata-phy"; - phys = <&psgtr 3 PHY_TYPE_SATA 1 2>; +&gem3 { /* required by spec */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem3_default>; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; + reset-delay-us = <2>; + + phy0: ethernet-phy@1 { + #phy-cells = <1>; + reg = <1>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,dp83867-rxctrl-strap-quirk; }; }; +}; - fragment4 { - target = <&zynqmp_dpsub>; - __overlay__ { - status = "disabled"; - phy-names = "dp-phy0", "dp-phy1"; - phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; +&pinctrl0 { /* required by spec */ + status = "okay"; + + pinctrl_uart1_default: uart1-default { + conf { + groups = "uart1_9_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + drive-strength = <12>; }; - }; - fragment9 { - target = <&zynqmp_dpdma>; - __overlay__ { - status = "okay"; + conf-rx { + pins = "MIO37"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO36"; + bias-disable; }; - }; - fragment10 { - target = <&usb0>; - __overlay__ { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0_default>; - usbhub: usb5744 { /* u43 */ - compatible = "microchip,usb5744"; - reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>; - }; + mux { + groups = "uart1_9_grp"; + function = "uart1"; }; }; - fragment11 { - target = <&dwc3_0>; - __overlay__ { - status = "okay"; - dr_mode = "host"; - snps,usb3_lpm_capable; - phy-names = "usb3-phy"; - phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; - maximum-speed = "super-speed"; + pinctrl_i2c1_default: i2c1-default { + conf { + groups = "i2c1_6_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux { + groups = "i2c1_6_grp"; + function = "i2c1"; }; }; - fragment12 { - target = <&sdhci1>; /* on CC with tuned parameters */ - __overlay__ { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhci1_default>; - /* - * SD 3.0 requires level shifter and this property - * should be removed if the board has level shifter and - * need to work in UHS mode - */ - no-1-8-v; - disable-wp; - xlnx,mio-bank = <1>; + pinctrl_i2c1_gpio: i2c1-gpio { + conf { + groups = "gpio0_24_grp", "gpio0_25_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux { + groups = "gpio0_24_grp", "gpio0_25_grp"; + function = "gpio0"; }; }; - fragment13 { - target = <&gem3>; /* required by spec */ - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gem3_default>; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; - reset-delay-us = <2>; - - phy0: ethernet-phy@1 { - #phy-cells = <1>; - reg = <1>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - ti,dp83867-rxctrl-strap-quirk; - }; - }; + pinctrl_gem3_default: gem3-default { + conf { + groups = "ethernet3_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO70", "MIO72", "MIO74"; + bias-high-impedance; + low-power-disable; + }; + + conf-bootstrap { + pins = "MIO71", "MIO73", "MIO75"; + bias-disable; + low-power-disable; + }; + + conf-tx { + pins = "MIO64", "MIO65", "MIO66", + "MIO67", "MIO68", "MIO69"; + bias-disable; + low-power-enable; + }; + + conf-mdio { + groups = "mdio3_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + bias-disable; + }; + + mux-mdio { + function = "mdio3"; + groups = "mdio3_0_grp"; + }; + + mux { + function = "ethernet3"; + groups = "ethernet3_0_grp"; }; }; - fragment14 { - target = <&pinctrl0>; /* required by spec */ - __overlay__ { - status = "okay"; - - pinctrl_uart1_default: uart1-default { - conf { - groups = "uart1_9_grp"; - slew-rate = <SLEW_RATE_SLOW>; - power-source = <IO_STANDARD_LVCMOS18>; - drive-strength = <12>; - }; - - conf-rx { - pins = "MIO37"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO36"; - bias-disable; - }; - - mux { - groups = "uart1_9_grp"; - function = "uart1"; - }; - }; - - pinctrl_i2c1_default: i2c1-default { - conf { - groups = "i2c1_6_grp"; - bias-pull-up; - slew-rate = <SLEW_RATE_SLOW>; - power-source = <IO_STANDARD_LVCMOS18>; - }; - - mux { - groups = "i2c1_6_grp"; - function = "i2c1"; - }; - }; - - pinctrl_i2c1_gpio: i2c1-gpio { - conf { - groups = "gpio0_24_grp", "gpio0_25_grp"; - slew-rate = <SLEW_RATE_SLOW>; - power-source = <IO_STANDARD_LVCMOS18>; - }; - - mux { - groups = "gpio0_24_grp", "gpio0_25_grp"; - function = "gpio0"; - }; - }; - - pinctrl_gem3_default: gem3-default { - conf { - groups = "ethernet3_0_grp"; - slew-rate = <SLEW_RATE_SLOW>; - power-source = <IO_STANDARD_LVCMOS18>; - }; - - conf-rx { - pins = "MIO70", "MIO72", "MIO74"; - bias-high-impedance; - low-power-disable; - }; - - conf-bootstrap { - pins = "MIO71", "MIO73", "MIO75"; - bias-disable; - low-power-disable; - }; - - conf-tx { - pins = "MIO64", "MIO65", "MIO66", - "MIO67", "MIO68", "MIO69"; - bias-disable; - low-power-enable; - }; - - conf-mdio { - groups = "mdio3_0_grp"; - slew-rate = <SLEW_RATE_SLOW>; - power-source = <IO_STANDARD_LVCMOS18>; - bias-disable; - }; - - mux-mdio { - function = "mdio3"; - groups = "mdio3_0_grp"; - }; - - mux { - function = "ethernet3"; - groups = "ethernet3_0_grp"; - }; - }; - - pinctrl_usb0_default: usb0-default { - conf { - groups = "usb0_0_grp"; - slew-rate = <SLEW_RATE_SLOW>; - power-source = <IO_STANDARD_LVCMOS18>; - }; - - conf-rx { - pins = "MIO52", "MIO53", "MIO55"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", - "MIO60", "MIO61", "MIO62", "MIO63"; - bias-disable; - }; - - mux { - groups = "usb0_0_grp"; - function = "usb0"; - }; - }; - - pinctrl_sdhci1_default: sdhci1-default { - conf { - groups = "sdio1_0_grp"; - slew-rate = <SLEW_RATE_SLOW>; - power-source = <IO_STANDARD_LVCMOS18>; - bias-disable; - }; - - conf-cd { - groups = "sdio1_cd_0_grp"; - bias-high-impedance; - bias-pull-up; - slew-rate = <SLEW_RATE_SLOW>; - power-source = <IO_STANDARD_LVCMOS18>; - }; - - mux-cd { - groups = "sdio1_cd_0_grp"; - function = "sdio1_cd"; - }; - - mux { - groups = "sdio1_0_grp"; - function = "sdio1"; - }; - }; + pinctrl_usb0_default: usb0-default { + conf { + groups = "usb0_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + }; + + mux { + groups = "usb0_0_grp"; + function = "usb0"; }; }; - fragment15 { - target = <&uart1>; - __overlay__ { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_default>; + + pinctrl_sdhci1_default: sdhci1-default { + conf { + groups = "sdio1_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + bias-disable; + }; + + conf-cd { + groups = "sdio1_cd_0_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux-cd { + groups = "sdio1_cd_0_grp"; + function = "sdio1_cd"; + }; + + mux { + groups = "sdio1_0_grp"; + function = "sdio1"; }; }; }; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; +}; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts index 6e46f5717b..b5443afff9 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts @@ -2,7 +2,7 @@ /* * dts file for KV260 revA Carrier Card * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> */ @@ -15,339 +15,304 @@ /dts-v1/; /plugin/; -/{ +&{/} { compatible = "xlnx,zynqmp-sk-kv260-rev1", - "xlnx,zynqmp-sk-kv260-revB", "xlnx,zynqmp-sk-kv260-revA", + "xlnx,zynqmp-sk-kv260-revB", "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp"; +}; - fragment1 { - target = <&i2c1>; /* I2C_SCK C23/C24 - MIO from SOM */ - - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1_default>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; - - u14: ina260@40 { /* u14 */ - compatible = "ti,ina260"; - #io-channel-cells = <1>; - label = "ina260-u14"; - reg = <0x40>; - }; - usbhub: usb5744@2d { /* u43 */ - compatible = "microchip,usb5744"; - reg = <0x2d>; - reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>; - }; - /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ - }; +&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + + u14: ina260@40 { /* u14 */ + compatible = "ti,ina260"; + #io-channel-cells = <1>; + label = "ina260-u14"; + reg = <0x40>; + }; + usbhub: usb5744@2d { /* u43 */ + compatible = "microchip,usb5744"; + reg = <0x2d>; + reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>; }; + /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ +}; - fragment1a { - target = <&amba>; - __overlay__ { - ina260-u14 { - compatible = "iio-hwmon"; - io-channels = <&u14 0>, <&u14 1>, <&u14 2>; - }; - - si5332_0: si5332_0 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; - - si5332_1: si5332_1 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - si5332_2: si5332_2 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; - - si5332_3: si5332_3 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - - si5332_4: si5332_4 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - - si5332_5: si5332_5 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - }; - }; +&amba { + ina260-u14 { + compatible = "iio-hwmon"; + io-channels = <&u14 0>, <&u14 1>, <&u14 2>; + }; + + si5332_0: si5332_0 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + si5332_1: si5332_1 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + si5332_2: si5332_2 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + si5332_3: si5332_3 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + si5332_4: si5332_4 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + si5332_5: si5332_5 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; }; +}; /* DP/USB 3.0 */ - fragment2 { - target = <&psgtr>; - __overlay__ { - status = "okay"; - /* pcie, usb3, sata */ - clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>; - clock-names = "ref0", "ref1", "ref2"; +&psgtr { + status = "okay"; + /* pcie, usb3, sata */ + clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>; + clock-names = "ref0", "ref1", "ref2"; +}; + +&zynqmp_dpsub { + status = "disabled"; + phy-names = "dp-phy0", "dp-phy1"; + phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; +}; + +&zynqmp_dpdma { + status = "okay"; +}; + +&usb0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + phy-names = "usb3-phy"; + phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; + maximum-speed = "super-speed"; +}; + +&sdhci1 { /* on CC with tuned parameters */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci1_default>; + /* + * SD 3.0 requires level shifter and this property + * should be removed if the board has level shifter and + * need to work in UHS mode + */ + no-1-8-v; + disable-wp; + xlnx,mio-bank = <1>; + clk-phase-sd-hs = <126>, <60>; + clk-phase-uhs-sdr25 = <120>, <60>; + clk-phase-uhs-ddr50 = <126>, <48>; +}; + +&gem3 { /* required by spec */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem3_default>; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; + reset-delay-us = <2>; + + phy0: ethernet-phy@1 { + #phy-cells = <1>; + reg = <1>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,dp83867-rxctrl-strap-quirk; }; }; +}; + +&pinctrl0 { /* required by spec */ + status = "okay"; - fragment4 { - target = <&zynqmp_dpsub>; - __overlay__ { - status = "disabled"; - phy-names = "dp-phy0", "dp-phy1"; - phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; + pinctrl_uart1_default: uart1-default { + conf { + groups = "uart1_9_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + drive-strength = <12>; }; - }; - fragment9 { - target = <&zynqmp_dpdma>; - __overlay__ { - status = "okay"; + conf-rx { + pins = "MIO37"; + bias-high-impedance; }; - }; - fragment10 { - target = <&usb0>; - __overlay__ { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0_default>; + conf-tx { + pins = "MIO36"; + bias-disable; + }; + + mux { + groups = "uart1_9_grp"; + function = "uart1"; }; }; - fragment11 { - target = <&dwc3_0>; - __overlay__ { - status = "okay"; - dr_mode = "host"; - snps,usb3_lpm_capable; - phy-names = "usb3-phy"; - phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; - maximum-speed = "super-speed"; + pinctrl_i2c1_default: i2c1-default { + conf { + groups = "i2c1_6_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux { + groups = "i2c1_6_grp"; + function = "i2c1"; }; }; - fragment12 { - target = <&sdhci1>; /* on CC with tuned parameters */ - __overlay__ { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhci1_default>; - /* - * SD 3.0 requires level shifter and this property - * should be removed if the board has level shifter and - * need to work in UHS mode - */ - no-1-8-v; - disable-wp; - xlnx,mio-bank = <1>; - clk-phase-sd-hs = <126>, <60>; - clk-phase-uhs-sdr25 = <120>, <60>; - clk-phase-uhs-ddr50 = <126>, <48>; + pinctrl_i2c1_gpio: i2c1-gpio { + conf { + groups = "gpio0_24_grp", "gpio0_25_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux { + groups = "gpio0_24_grp", "gpio0_25_grp"; + function = "gpio0"; }; }; - fragment13 { - target = <&gem3>; /* required by spec */ - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gem3_default>; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; - reset-delay-us = <2>; - - phy0: ethernet-phy@1 { - #phy-cells = <1>; - reg = <1>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - ti,dp83867-rxctrl-strap-quirk; - }; - }; + pinctrl_gem3_default: gem3-default { + conf { + groups = "ethernet3_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO70", "MIO72", "MIO74"; + bias-high-impedance; + low-power-disable; + }; + + conf-bootstrap { + pins = "MIO71", "MIO73", "MIO75"; + bias-disable; + low-power-disable; + }; + + conf-tx { + pins = "MIO64", "MIO65", "MIO66", + "MIO67", "MIO68", "MIO69"; + bias-disable; + low-power-enable; + }; + + conf-mdio { + groups = "mdio3_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + bias-disable; + }; + + mux-mdio { + function = "mdio3"; + groups = "mdio3_0_grp"; + }; + + mux { + function = "ethernet3"; + groups = "ethernet3_0_grp"; }; }; - fragment14 { - target = <&pinctrl0>; /* required by spec */ - __overlay__ { - status = "okay"; - - pinctrl_uart1_default: uart1-default { - conf { - groups = "uart1_9_grp"; - slew-rate = <SLEW_RATE_SLOW>; - power-source = <IO_STANDARD_LVCMOS18>; - drive-strength = <12>; - }; - - conf-rx { - pins = "MIO37"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO36"; - bias-disable; - }; - - mux { - groups = "uart1_9_grp"; - function = "uart1"; - }; - }; - - pinctrl_i2c1_default: i2c1-default { - conf { - groups = "i2c1_6_grp"; - bias-pull-up; - slew-rate = <SLEW_RATE_SLOW>; - power-source = <IO_STANDARD_LVCMOS18>; - }; - - mux { - groups = "i2c1_6_grp"; - function = "i2c1"; - }; - }; - - pinctrl_i2c1_gpio: i2c1-gpio { - conf { - groups = "gpio0_24_grp", "gpio0_25_grp"; - slew-rate = <SLEW_RATE_SLOW>; - power-source = <IO_STANDARD_LVCMOS18>; - }; - - mux { - groups = "gpio0_24_grp", "gpio0_25_grp"; - function = "gpio0"; - }; - }; - - pinctrl_gem3_default: gem3-default { - conf { - groups = "ethernet3_0_grp"; - slew-rate = <SLEW_RATE_SLOW>; - power-source = <IO_STANDARD_LVCMOS18>; - }; - - conf-rx { - pins = "MIO70", "MIO72", "MIO74"; - bias-high-impedance; - low-power-disable; - }; - - conf-bootstrap { - pins = "MIO71", "MIO73", "MIO75"; - bias-disable; - low-power-disable; - }; - - conf-tx { - pins = "MIO64", "MIO65", "MIO66", - "MIO67", "MIO68", "MIO69"; - bias-disable; - low-power-enable; - }; - - conf-mdio { - groups = "mdio3_0_grp"; - slew-rate = <SLEW_RATE_SLOW>; - power-source = <IO_STANDARD_LVCMOS18>; - bias-disable; - }; - - mux-mdio { - function = "mdio3"; - groups = "mdio3_0_grp"; - }; - - mux { - function = "ethernet3"; - groups = "ethernet3_0_grp"; - }; - }; - - pinctrl_usb0_default: usb0-default { - conf { - groups = "usb0_0_grp"; - slew-rate = <SLEW_RATE_SLOW>; - power-source = <IO_STANDARD_LVCMOS18>; - }; - - conf-rx { - pins = "MIO52", "MIO53", "MIO55"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", - "MIO60", "MIO61", "MIO62", "MIO63"; - bias-disable; - }; - - mux { - groups = "usb0_0_grp"; - function = "usb0"; - }; - }; - - pinctrl_sdhci1_default: sdhci1-default { - conf { - groups = "sdio1_0_grp"; - slew-rate = <SLEW_RATE_SLOW>; - power-source = <IO_STANDARD_LVCMOS18>; - bias-disable; - }; - - conf-cd { - groups = "sdio1_cd_0_grp"; - bias-high-impedance; - bias-pull-up; - slew-rate = <SLEW_RATE_SLOW>; - power-source = <IO_STANDARD_LVCMOS18>; - }; - - mux-cd { - groups = "sdio1_cd_0_grp"; - function = "sdio1_cd"; - }; - - mux { - groups = "sdio1_0_grp"; - function = "sdio1"; - }; - }; + pinctrl_usb0_default: usb0-default { + conf { + groups = "usb0_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + }; + + mux { + groups = "usb0_0_grp"; + function = "usb0"; }; }; - fragment15 { - target = <&uart1>; - __overlay__ { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_default>; + + pinctrl_sdhci1_default: sdhci1-default { + conf { + groups = "sdio1_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + bias-disable; + }; + + conf-cd { + groups = "sdio1_cd_0_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux-cd { + groups = "sdio1_cd_0_grp"; + function = "sdio1_cd"; + }; + + mux { + groups = "sdio1_0_grp"; + function = "sdio1"; }; }; }; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; +}; diff --git a/arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi b/arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi index 3f01233cc5..467df9f23a 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi +++ b/arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP K26/KV260 SD wiring * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> */ diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index e4cf382a49..b613ab2342 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP SM-K26 rev1/B/A * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> */ @@ -22,11 +22,12 @@ "xlnx,zynqmp"; aliases { - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; + nvmem0 = &eeprom; + nvmem1 = &eeprom_cc; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; @@ -36,8 +37,6 @@ spi2 = &spi1; usb0 = &usb0; usb1 = &usb1; - nvmem0 = &eeprom; - nvmem1 = &eeprom_cc; }; chosen { diff --git a/arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi b/arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi index 8e9106792f..34e6328fb6 100644 --- a/arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi +++ b/arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP Z2-VSOM * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> */ diff --git a/arch/arm/dts/zynqmp-smk-k26-revA.dts b/arch/arm/dts/zynqmp-smk-k26-revA.dts index 300edc8800..c70966c1f3 100644 --- a/arch/arm/dts/zynqmp-smk-k26-revA.dts +++ b/arch/arm/dts/zynqmp-smk-k26-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> */ diff --git a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts index a377f27c50..6ec96e0e8c 100644 --- a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts +++ b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts @@ -19,7 +19,6 @@ "topic,miamimp", "xlnx,zynqmp"; aliases { - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; diff --git a/arch/arm/dts/zynqmp-zc1232-revA.dts b/arch/arm/dts/zynqmp-zc1232-revA.dts index ef7cf0a36b..7543855c9f 100644 --- a/arch/arm/dts/zynqmp-zc1232-revA.dts +++ b/arch/arm/dts/zynqmp-zc1232-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZC1232 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> */ @@ -11,7 +11,6 @@ #include "zynqmp.dtsi" #include "zynqmp-clk-ccf.dtsi" -#include <dt-bindings/phy/phy.h> / { model = "ZynqMP ZC1232 RevA"; diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index 039a8da1a9..b92a2ee3e6 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> */ @@ -21,7 +21,6 @@ aliases { ethernet0 = &gem3; - gpio0 = &gpio; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; @@ -60,13 +59,6 @@ }; }; -&psgtr { - status = "okay"; - /* dp, usb3, sata */ - clocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>; - clock-names = "ref1", "ref2", "ref3"; -}; - &fpd_dma_chan1 { status = "okay"; }; @@ -345,6 +337,13 @@ }; }; +&psgtr { + status = "okay"; + /* dp, usb3, sata */ + clocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>; + clock-names = "ref1", "ref2", "ref3"; +}; + &qspi { status = "okay"; flash@0 { @@ -433,6 +432,7 @@ snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; + maximum-speed = "super-speed"; }; &zynqmp_dpdma { @@ -441,5 +441,7 @@ &zynqmp_dpsub { status = "okay"; + phy-names = "dp-phy0", "dp-phy1"; + phys = <&psgtr 1 PHY_TYPE_DP 0 0>, + <&psgtr 0 PHY_TYPE_DP 1 1>; }; - diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index d6e9248033..5b689dbd09 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> */ @@ -19,10 +19,7 @@ compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { - can0 = &can0; - can1 = &can1; ethernet0 = &gem2; - gpio0 = &gpio; i2c0 = &i2c0; rtc0 = &rtc; serial0 = &uart0; @@ -538,6 +535,8 @@ &dwc3_1 { status = "okay"; dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; }; &uart0 { diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts index c7de59e1e9..344323ab7f 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm017-dc3 * - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> */ @@ -11,6 +11,7 @@ #include "zynqmp.dtsi" #include "zynqmp-clk-ccf.dtsi" +#include <dt-bindings/phy/phy.h> / { model = "ZynqMP zc1751-xm017-dc3 RevA"; @@ -18,7 +19,6 @@ aliases { ethernet0 = &gem0; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; @@ -38,6 +38,18 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + + clock_si5338_2: clk26 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + clock_si5338_3: clk125 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; }; &fpd_dma_chan1 { @@ -167,6 +179,13 @@ }; }; +&psgtr { + status = "okay"; + /* usb3, sata */ + clocks = <&clock_si5338_2>, <&clock_si5338_3>; + clock-names = "ref2", "ref3"; +}; + &rtc { status = "okay"; }; @@ -182,6 +201,8 @@ ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + phy-names = "sata-phy"; + phys = <&psgtr 2 PHY_TYPE_SATA 0 3>; }; &sdhci1 { /* emmc with some settings */ @@ -200,11 +221,27 @@ &usb0 { status = "okay"; +}; + +&dwc3_0 { + status = "okay"; dr_mode = "host"; + snps,usb3_lpm_capable; + phy-names = "usb3-phy"; + phys = <&psgtr 0 PHY_TYPE_USB3 0 2>; + maximum-speed = "super-speed"; }; /* ULPI SMSC USB3320 */ &usb1 { status = "okay"; +}; + +&dwc3_1 { + status = "okay"; dr_mode = "host"; + snps,usb3_lpm_capable; + phy-names = "usb3-phy"; + phys = <&psgtr 3 PHY_TYPE_USB3 1 2>; + maximum-speed = "super-speed"; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts index aadda179c3..f420f83ad2 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm018-dc4 * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> */ @@ -17,13 +17,10 @@ compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { - can0 = &can0; - can1 = &can1; ethernet0 = &gem0; ethernet1 = &gem1; ethernet2 = &gem2; ethernet3 = &gem3; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; rtc0 = &rtc; @@ -115,14 +112,6 @@ status = "okay"; }; -&zynqmp_dpsub { - status = "okay"; -}; - -&zynqmp_dpdma { - status = "okay"; -}; - &gem0 { status = "okay"; phy-mode = "rgmii-id"; @@ -221,3 +210,11 @@ &watchdog0 { status = "okay"; }; + +&zynqmp_dpdma { + status = "okay"; +}; + +&zynqmp_dpsub { + status = "okay"; +}; diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts index 46b27a0009..ae2d03d983 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm019-dc5 * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015 - 2021, Xilinx, Inc. * * Siva Durga Prasad <siva.durga.paladugu@xilinx.com> * Michal Simek <michal.simek@xilinx.com> @@ -21,7 +21,6 @@ aliases { ethernet0 = &gem1; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index b83696cccd..2d61577478 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> * Nathalie Chan King Choy @@ -23,7 +23,6 @@ compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; aliases { - gpio0 = &gpio; i2c0 = &i2c1; rtc0 = &rtc; serial0 = &uart1; @@ -132,13 +131,13 @@ io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; }; - si5335a_0: clk26 { + si5335_0: si5335_0 { /* clk0_usb - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; - si5335a_1: clk27 { + si5335_1: si5335_1 { /* clk1_dp - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; @@ -485,8 +484,8 @@ &psgtr { status = "okay"; - /* usb3, dps */ - clocks = <&si5335a_0>, <&si5335a_1>; + /* usb3, dp */ + clocks = <&si5335_0>, <&si5335_1>; clock-names = "ref0", "ref1"; }; diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index ec61b7089d..c1af5fc635 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> */ @@ -22,10 +22,10 @@ aliases { ethernet0 = &gem3; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; + nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; @@ -37,7 +37,6 @@ chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; - xlnx,eeprom = &eeprom; }; memory@0 { @@ -605,15 +604,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <4>; - si5328: clock-generator@69 {/* SI5328 - u20 */ - compatible = "silabs,si5328"; - reg = <0x69>; - /* - * Chip has interrupt present connected to PL - * interrupt-parent = <&>; - * interrupts = <>; - */ - }; + /* SI5328 - u20 */ }; /* 5 - 7 unconnected */ }; diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index c25ac9af48..7e5eca82fd 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> */ @@ -21,9 +21,9 @@ aliases { ethernet0 = &gem3; - gpio0 = &gpio; i2c0 = &i2c1; mmc0 = &sdhci1; + nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; @@ -165,10 +165,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <1>; - clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ - compatible = "idt,8t49n287"; - reg = <0x6c>; - }; + /* 8T49N287 - u182 */ }; i2c@2 { @@ -423,6 +420,13 @@ }; }; +&psgtr { + status = "okay"; + /* nc, sata, usb3, dp */ + clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; + clock-names = "ref1", "ref2", "ref3"; +}; + &qspi { status = "okay"; flash@0 { @@ -452,13 +456,6 @@ }; }; -&psgtr { - status = "okay"; - /* nc, sata, usb3, dp */ - clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; - clock-names = "ref1", "ref2", "ref3"; -}; - &rtc { status = "okay"; }; diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index ce9d8fb3b8..f4ebcbb318 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> */ @@ -21,9 +21,9 @@ aliases { ethernet0 = &gem3; - gpio0 = &gpio; i2c0 = &i2c1; mmc0 = &sdhci1; + nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; @@ -35,7 +35,6 @@ chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; - xlnx,eeprom = &eeprom; }; memory@0 { @@ -190,10 +189,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <1>; - clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ - compatible = "idt,8t49n287"; - reg = <0x6c>; - }; + /* 8T49N287 - u182 */ }; i2c@2 { @@ -436,6 +432,13 @@ }; }; +&psgtr { + status = "okay"; + /* nc, sata, usb3, dp */ + clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; + clock-names = "ref1", "ref2", "ref3"; +}; + &qspi { status = "okay"; flash@0 { @@ -469,13 +472,6 @@ status = "okay"; }; -&psgtr { - status = "okay"; - /* nc, sata, usb3, dp */ - clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; - clock-names = "ref1", "ref2", "ref3"; -}; - &sata { status = "okay"; /* SATA OOB timing settings */ diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index ae20e581c0..ac6689c167 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> */ @@ -22,10 +22,10 @@ aliases { ethernet0 = &gem3; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; + nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; @@ -37,7 +37,6 @@ chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; - xlnx,eeprom = &eeprom; }; memory@0 { @@ -163,18 +162,6 @@ status = "okay"; }; -&zynqmp_dpdma { - status = "okay"; -}; - -&zynqmp_dpsub { - status = "okay"; - phy-names = "dp-phy0", "dp-phy1"; - phys = <&psgtr 1 PHY_TYPE_DP 0 3>, - <&psgtr 0 PHY_TYPE_DP 1 3>; -}; - -/* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { status = "okay"; }; @@ -606,25 +593,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <4>; - si5328: clock-generator@69 {/* SI5328 - u20 */ - reg = <0x69>; - /* - * Chip has interrupt present connected to PL - * interrupt-parent = <&>; - * interrupts = <>; - */ - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <1>; - clocks = <&refhdmi>; - clock-names = "xtal"; - clock-output-names = "si5328"; - - si5328_clk: clk0@0 { - reg = <0>; - clock-frequency = <27000000>; - }; - }; + /* SI5328 - u20 */ }; i2c@5 { #address-cells = <1>; @@ -1051,8 +1020,20 @@ snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; + maximum-speed = "super-speed"; }; &watchdog0 { status = "okay"; }; + +&zynqmp_dpdma { + status = "okay"; +}; + +&zynqmp_dpsub { + status = "okay"; + phy-names = "dp-phy0", "dp-phy1"; + phys = <&psgtr 1 PHY_TYPE_DP 0 3>, + <&psgtr 0 PHY_TYPE_DP 1 3>; +}; diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index d564f74344..8d57ca2b3b 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> */ @@ -22,10 +22,10 @@ aliases { ethernet0 = &gem3; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; + nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; @@ -36,7 +36,6 @@ chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; - xlnx,eeprom = &eeprom; }; memory@0 { @@ -481,10 +480,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <4>; - si5382: clock-generator@69 { /* SI5382 - u48 */ - compatible = "silabs,si5382"; - reg = <0x69>; - }; + /* SI5382 - u48 */ }; i2c@5 { #address-cells = <1>; @@ -775,8 +771,8 @@ &psgtr { status = "okay"; - /* nc, sata, usb3, dp */ - clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; + /* nc, dp, usb3, sata */ + clocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>; clock-names = "ref1", "ref2", "ref3"; }; @@ -861,6 +857,7 @@ snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; + maximum-speed = "super-speed"; }; &zynqmp_dpdma { diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts index cdd5c34187..10d8bc8f9a 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU1275 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> * Siva Durga Prasad Paladugu <sivadur@xilinx.com> @@ -39,6 +39,10 @@ status = "okay"; }; +&gpio { + status = "okay"; +}; + &qspi { status = "okay"; flash@0 { diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts index 1de890c30f..97ae1b2d2d 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revB.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU1275 RevB * - * (C) Copyright 2018 - 2020, Xilinx, Inc. + * (C) Copyright 2018 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> * Siva Durga Prasad Paladugu <sivadur@xilinx.com> @@ -64,6 +64,10 @@ }; }; +&gpio { + status = "okay"; +}; + &qspi { status = "okay"; flash@0 { diff --git a/arch/arm/dts/zynqmp-zcu1285-revA.dts b/arch/arm/dts/zynqmp-zcu1285-revA.dts index 21d62e993a..eaf99a9fa8 100644 --- a/arch/arm/dts/zynqmp-zcu1285-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU1285 RevA * - * (C) Copyright 2018 - 2020, Xilinx, Inc. + * (C) Copyright 2018 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> * Siva Durga Prasad Paladugu <sivadur@xilinx.com> @@ -245,6 +245,10 @@ }; }; +&gpio { + status = "okay"; +}; + &qspi { status = "okay"; flash@0 { diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 880281d4e7..d3e20ae85d 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU208 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> */ @@ -22,10 +22,10 @@ aliases { ethernet0 = &gem3; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; + nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; @@ -36,7 +36,6 @@ chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; - xlnx,eeprom = &eeprom; }; memory@0 { @@ -651,9 +650,9 @@ &psgtr { status = "okay"; - /* pcie, sata, usb3, dp */ - clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; - clock-names = "ref0", "ref1", "ref2", "ref3"; + /* nc, nc, usb3, sata */ + clocks = <&si5341 0 2>, <&si5341 0 3>; + clock-names = "ref2", "ref3"; }; &rtc { @@ -701,4 +700,5 @@ snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; + maximum-speed = "super-speed"; }; diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index f899226ae1..ae7c181968 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU216 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> */ @@ -22,10 +22,10 @@ aliases { ethernet0 = &gem3; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; + nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; @@ -36,7 +36,6 @@ chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; - xlnx,eeprom = <&eeprom>; }; memory@0 { @@ -132,9 +131,9 @@ &psgtr { status = "okay"; - /* pcie, sata, usb3, dp */ - clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; - clock-names = "ref0", "ref1", "ref2", "ref3"; + /* nc, nc, usb3, sata */ + clocks = <&si5341 0 2>, <&si5341 0 3>; + clock-names = "ref2", "ref3"; }; &dcc { @@ -705,4 +704,5 @@ snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; + maximum-speed = "super-speed"; }; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 84d9770225..1332f5373f 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2020, Xilinx, Inc. + * (C) Copyright 2014 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> * @@ -100,7 +100,7 @@ }; }; - zynqmp_ipi { + zynqmp_ipi: zynqmp_ipi { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; @@ -246,6 +246,7 @@ cci: cci@fd6e0000 { compatible = "arm,cci-400"; + status = "disabled"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; @@ -647,6 +648,8 @@ <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; + #stream-id-cells = <1>; + iommus = <&smmu 0x4d0>; power-domains = <&zynqmp_firmware PD_PCIE>; pcie_intc: legacy-interrupt-controller { interrupt-controller; @@ -688,7 +691,7 @@ interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; - calibration = <0x8000>; + calibration = <0x7FFF>; }; sata: ahci@fd0c0000 { @@ -698,6 +701,7 @@ interrupt-parent = <&gic>; interrupts = <0 133 4>; power-domains = <&zynqmp_firmware PD_SATA>; + resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; #stream-id-cells = <4>; iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; @@ -715,8 +719,6 @@ xlnx,device_id = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x870>; - nvmem-cells = <&soc_revision>; - nvmem-cell-names = "soc_revision"; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; power-domains = <&zynqmp_firmware PD_SD_0>; @@ -733,8 +735,6 @@ xlnx,device_id = <1>; #stream-id-cells = <1>; iommus = <&smmu 0x871>; - nvmem-cells = <&soc_revision>; - nvmem-cell-names = "soc_revision"; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; power-domains = <&zynqmp_firmware PD_SD_1>; @@ -848,20 +848,26 @@ reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_0>; + resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, + <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, + <&zynqmp_reset ZYNQMP_RESET_USB0_APB>; + reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; ranges; - nvmem-cells = <&soc_revision>; - nvmem-cell-names = "soc_revision"; dwc3_0: dwc3@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; - interrupts = <0 65 4>, <0 69 4>; + interrupt-names = "dwc_usb3", "otg", "hiber"; + interrupts = <0 65 4>, <0 69 4>, <0 75 4>; #stream-id-cells = <1>; iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; + snps,enable_guctl1_resume_quirk; + snps,enable_guctl1_ipd_quirk; + snps,xhci-stream-quirk; /* dma-coherent; */ }; }; @@ -874,20 +880,26 @@ reg = <0x0 0xff9e0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_1>; + resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, + <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, + <&zynqmp_reset ZYNQMP_RESET_USB1_APB>; + reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; ranges; - nvmem-cells = <&soc_revision>; - nvmem-cell-names = "soc_revision"; dwc3_1: dwc3@fe300000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; - interrupts = <0 70 4>, <0 74 4>; + interrupt-names = "dwc_usb3", "otg", "hiber"; + interrupts = <0 70 4>, <0 74 4>, <0 76 4>; #stream-id-cells = <1>; iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; + snps,enable_guctl1_resume_quirk; + snps,enable_guctl1_ipd_quirk; + snps,xhci-stream-quirk; /* dma-coherent; */ }; }; |