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-rw-r--r--arch/mips/dts/brcm,bcm3380.dtsi17
-rw-r--r--arch/mips/dts/brcm,bcm63268.dtsi38
-rw-r--r--arch/mips/dts/brcm,bcm6328.dtsi24
-rw-r--r--arch/mips/dts/brcm,bcm6338.dtsi17
-rw-r--r--arch/mips/dts/brcm,bcm6348.dtsi17
-rw-r--r--arch/mips/dts/brcm,bcm6358.dtsi17
-rw-r--r--arch/mips/dts/comtrend,ar-5387un.dts12
-rw-r--r--arch/mips/dts/netgear,cg3100d.dts12
-rw-r--r--arch/mips/dts/sagem,f@st1704.dts12
-rw-r--r--arch/mips/mach-ath79/ar934x/clk.c2
10 files changed, 167 insertions, 1 deletions
diff --git a/arch/mips/dts/brcm,bcm3380.dtsi b/arch/mips/dts/brcm,bcm3380.dtsi
index 64245eb048..f83a6ea8df 100644
--- a/arch/mips/dts/brcm,bcm3380.dtsi
+++ b/arch/mips/dts/brcm,bcm3380.dtsi
@@ -12,6 +12,10 @@
/ {
compatible = "brcm,bcm3380";
+ aliases {
+ spi0 = &spi;
+ };
+
cpus {
reg = <0x14e00000 0x4>;
#address-cells = <1>;
@@ -142,6 +146,19 @@
status = "disabled";
};
+ spi: spi@14e02000 {
+ compatible = "brcm,bcm6358-spi";
+ reg = <0x14e02000 0x70c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&periph_clk0 BCM3380_CLK0_SPI>;
+ resets = <&periph_rst0 BCM3380_RST0_SPI>;
+ spi-max-frequency = <25000000>;
+ num-cs = <6>;
+
+ status = "disabled";
+ };
+
leds: led-controller@14e00f00 {
compatible = "brcm,bcm6328-leds";
reg = <0x14e00f00 0x1c>;
diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi
index 113a96bef8..4d4e36cccc 100644
--- a/arch/mips/dts/brcm,bcm63268.dtsi
+++ b/arch/mips/dts/brcm,bcm63268.dtsi
@@ -13,6 +13,11 @@
/ {
compatible = "brcm,bcm63268";
+ aliases {
+ spi0 = &lsspi;
+ spi1 = &hsspi;
+ };
+
cpus {
reg = <0x10000000 0x4>;
#address-cells = <1>;
@@ -40,6 +45,12 @@
#size-cells = <1>;
u-boot,dm-pre-reloc;
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <400000000>;
+ };
+
periph_osc: periph-osc {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -136,6 +147,33 @@
#power-domain-cells = <1>;
};
+ lsspi: spi@10000800 {
+ compatible = "brcm,bcm6358-spi";
+ reg = <0x10000800 0x70c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&periph_clk BCM63268_CLK_SPI>;
+ resets = <&periph_rst BCM63268_RST_SPI>;
+ spi-max-frequency = <20000000>;
+ num-cs = <8>;
+
+ status = "disabled";
+ };
+
+ hsspi: spi@10001000 {
+ compatible = "brcm,bcm6328-hsspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x10001000 0x600>;
+ clocks = <&periph_clk BCM63268_CLK_HSSPI>, <&hsspi_pll>;
+ clock-names = "hsspi", "pll";
+ resets = <&periph_rst BCM63268_RST_SPI>;
+ spi-max-frequency = <50000000>;
+ num-cs = <8>;
+
+ status = "disabled";
+ };
+
leds: led-controller@10001900 {
compatible = "brcm,bcm6328-leds";
reg = <0x10001900 0x24>;
diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi
index a996075743..67d9278be4 100644
--- a/arch/mips/dts/brcm,bcm6328.dtsi
+++ b/arch/mips/dts/brcm,bcm6328.dtsi
@@ -13,6 +13,10 @@
/ {
compatible = "brcm,bcm6328";
+ aliases {
+ spi0 = &spi;
+ };
+
cpus {
reg = <0x10000000 0x4>;
#address-cells = <1>;
@@ -40,6 +44,12 @@
#size-cells = <1>;
u-boot,dm-pre-reloc;
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <133333333>;
+ };
+
periph_osc: periph-osc {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -123,6 +133,20 @@
status = "disabled";
};
+ spi: spi@10001000 {
+ compatible = "brcm,bcm6328-hsspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x10001000 0x600>;
+ clocks = <&periph_clk BCM6328_CLK_HSSPI>, <&hsspi_pll>;
+ clock-names = "hsspi", "pll";
+ resets = <&periph_rst BCM6328_RST_SPI>;
+ spi-max-frequency = <33333334>;
+ num-cs = <3>;
+
+ status = "disabled";
+ };
+
periph_pwr: power-controller@10001848 {
compatible = "brcm,bcm6328-power-domain";
reg = <0x10001848 0x4>;
diff --git a/arch/mips/dts/brcm,bcm6338.dtsi b/arch/mips/dts/brcm,bcm6338.dtsi
index eb51a4372b..0cab44cb8d 100644
--- a/arch/mips/dts/brcm,bcm6338.dtsi
+++ b/arch/mips/dts/brcm,bcm6338.dtsi
@@ -12,6 +12,10 @@
/ {
compatible = "brcm,bcm6338";
+ aliases {
+ spi0 = &spi;
+ };
+
cpus {
reg = <0xfffe0000 0x4>;
#address-cells = <1>;
@@ -109,6 +113,19 @@
status = "disabled";
};
+ spi: spi@fffe0c00 {
+ compatible = "brcm,bcm6348-spi";
+ reg = <0xfffe0c00 0xc0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&periph_clk BCM6338_CLK_SPI>;
+ resets = <&periph_rst BCM6338_RST_SPI>;
+ spi-max-frequency = <20000000>;
+ num-cs = <4>;
+
+ status = "disabled";
+ };
+
memory-controller@fffe3100 {
compatible = "brcm,bcm6338-mc";
reg = <0xfffe3100 0x38>;
diff --git a/arch/mips/dts/brcm,bcm6348.dtsi b/arch/mips/dts/brcm,bcm6348.dtsi
index 711b643b5a..540b9fea5b 100644
--- a/arch/mips/dts/brcm,bcm6348.dtsi
+++ b/arch/mips/dts/brcm,bcm6348.dtsi
@@ -12,6 +12,10 @@
/ {
compatible = "brcm,bcm6348";
+ aliases {
+ spi0 = &spi;
+ };
+
cpus {
reg = <0xfffe0000 0x4>;
#address-cells = <1>;
@@ -118,6 +122,19 @@
status = "disabled";
};
+ spi: spi@fffe0c00 {
+ compatible = "brcm,bcm6348-spi";
+ reg = <0xfffe0c00 0xc0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&periph_clk BCM6348_CLK_SPI>;
+ resets = <&periph_rst BCM6348_RST_SPI>;
+ spi-max-frequency = <20000000>;
+ num-cs = <4>;
+
+ status = "disabled";
+ };
+
memory-controller@fffe2300 {
compatible = "brcm,bcm6338-mc";
reg = <0xfffe2300 0x38>;
diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi
index 4f63cf80e0..1662783279 100644
--- a/arch/mips/dts/brcm,bcm6358.dtsi
+++ b/arch/mips/dts/brcm,bcm6358.dtsi
@@ -12,6 +12,10 @@
/ {
compatible = "brcm,bcm6358";
+ aliases {
+ spi0 = &spi;
+ };
+
cpus {
reg = <0xfffe0000 0x4>;
#address-cells = <1>;
@@ -142,6 +146,19 @@
status = "disabled";
};
+ spi: spi@fffe0800 {
+ compatible = "brcm,bcm6358-spi";
+ reg = <0xfffe0800 0x70c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&periph_clk BCM6358_CLK_SPI>;
+ resets = <&periph_rst BCM6358_RST_SPI>;
+ spi-max-frequency = <20000000>;
+ num-cs = <4>;
+
+ status = "disabled";
+ };
+
memory-controller@fffe1200 {
compatible = "brcm,bcm6358-mc";
reg = <0xfffe1200 0x4c>;
diff --git a/arch/mips/dts/comtrend,ar-5387un.dts b/arch/mips/dts/comtrend,ar-5387un.dts
index 73f2b49b76..6067881a78 100644
--- a/arch/mips/dts/comtrend,ar-5387un.dts
+++ b/arch/mips/dts/comtrend,ar-5387un.dts
@@ -51,6 +51,18 @@
};
};
+&spi {
+ status = "okay";
+
+ spi-flash@0 {
+ compatible = "spi-flash";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <33333334>;
+ };
+};
+
&uart0 {
u-boot,dm-pre-reloc;
status = "okay";
diff --git a/arch/mips/dts/netgear,cg3100d.dts b/arch/mips/dts/netgear,cg3100d.dts
index db1e2e7616..5f85c7346f 100644
--- a/arch/mips/dts/netgear,cg3100d.dts
+++ b/arch/mips/dts/netgear,cg3100d.dts
@@ -90,6 +90,18 @@
status = "okay";
};
+&spi {
+ status = "okay";
+
+ spi-flash@0 {
+ compatible = "spi-flash";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <25000000>;
+ };
+};
+
&uart0 {
u-boot,dm-pre-reloc;
status = "okay";
diff --git a/arch/mips/dts/sagem,f@st1704.dts b/arch/mips/dts/sagem,f@st1704.dts
index be15fe5551..dd0e5b8b7c 100644
--- a/arch/mips/dts/sagem,f@st1704.dts
+++ b/arch/mips/dts/sagem,f@st1704.dts
@@ -44,6 +44,18 @@
status = "okay";
};
+&spi {
+ status = "okay";
+
+ spi-flash@0 {
+ compatible = "spi-flash";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ };
+};
+
&uart0 {
u-boot,dm-pre-reloc;
status = "okay";
diff --git a/arch/mips/mach-ath79/ar934x/clk.c b/arch/mips/mach-ath79/ar934x/clk.c
index 9b41d3de60..ba2243c9be 100644
--- a/arch/mips/mach-ath79/ar934x/clk.c
+++ b/arch/mips/mach-ath79/ar934x/clk.c
@@ -90,7 +90,7 @@ static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val)
setbits_be32(pll_reg_base + 0x8, BIT(30));
udelay(5);
- wait_for_bit("clk", pll_reg_base + 0xc, BIT(3), 1, 10, 0);
+ wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0);
clrbits_be32(pll_reg_base + 0x8, BIT(30));
udelay(5);
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-27 07:17:51 +0300