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path: root/drivers/clk/rockchip/clk_rk3288.c
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Diffstat (limited to 'drivers/clk/rockchip/clk_rk3288.c')
-rw-r--r--drivers/clk/rockchip/clk_rk3288.c42
1 files changed, 21 insertions, 21 deletions
diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index 85d1b67e43..cc1c1e81e9 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -14,7 +14,7 @@
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/cru_rk3288.h>
+#include <asm/arch-rockchip/cru.h>
#include <asm/arch-rockchip/grf_rk3288.h>
#include <asm/arch-rockchip/hardware.h>
#include <dt-bindings/clock/rk3288-cru.h>
@@ -141,7 +141,7 @@ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
-static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
+static int rkclk_set_pll(struct rockchip_cru *cru, enum rk_clk_id clk_id,
const struct pll_div *div)
{
int pll_id = rk_pll_id(clk_id);
@@ -172,7 +172,7 @@ static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
return 0;
}
-static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,
+static int rkclk_configure_ddr(struct rockchip_cru *cru, struct rk3288_grf *grf,
unsigned int hz)
{
static const struct pll_div dpll_cfg[] = {
@@ -295,7 +295,7 @@ static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
return 0;
}
-static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq)
+static int rockchip_mac_set_clk(struct rockchip_cru *cru, uint freq)
{
ulong ret;
@@ -333,7 +333,7 @@ static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq)
return ret;
}
-static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
+static int rockchip_vop_set_clk(struct rockchip_cru *cru, struct rk3288_grf *grf,
int periph, unsigned int rate_hz)
{
struct pll_div npll_config = {0};
@@ -384,7 +384,7 @@ static u32 rockchip_clk_gcd(u32 a, u32 b)
return a;
}
-static ulong rockchip_i2s_get_clk(struct rk3288_cru *cru, uint gclk_rate)
+static ulong rockchip_i2s_get_clk(struct rockchip_cru *cru, uint gclk_rate)
{
unsigned long long rate;
uint val;
@@ -400,7 +400,7 @@ static ulong rockchip_i2s_get_clk(struct rk3288_cru *cru, uint gclk_rate)
return (ulong)rate;
}
-static ulong rockchip_i2s_set_clk(struct rk3288_cru *cru, uint gclk_rate,
+static ulong rockchip_i2s_set_clk(struct rockchip_cru *cru, uint gclk_rate,
uint freq)
{
int n, d;
@@ -418,7 +418,7 @@ static ulong rockchip_i2s_set_clk(struct rk3288_cru *cru, uint gclk_rate,
}
#endif /* CONFIG_SPL_BUILD */
-static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
+static void rkclk_init(struct rockchip_cru *cru, struct rk3288_grf *grf)
{
u32 aclk_div;
u32 hclk_div;
@@ -492,7 +492,7 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
}
-void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
+void rk3288_clk_configure_cpu(struct rockchip_cru *cru, struct rk3288_grf *grf)
{
/* pll enter slow-mode */
rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
@@ -534,7 +534,7 @@ void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
}
/* Get pll rate by id */
-static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
+static uint32_t rkclk_pll_get_rate(struct rockchip_cru *cru,
enum rk_clk_id clk_id)
{
uint32_t nr, no, nf;
@@ -567,7 +567,7 @@ static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
}
}
-static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
+static ulong rockchip_mmc_get_clk(struct rockchip_cru *cru, uint gclk_rate,
int periph)
{
uint src_rate;
@@ -601,7 +601,7 @@ static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
return DIV_TO_RATE(src_rate, div);
}
-static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
+static ulong rockchip_mmc_set_clk(struct rockchip_cru *cru, uint gclk_rate,
int periph, uint freq)
{
int src_clk_div;
@@ -651,7 +651,7 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
return rockchip_mmc_get_clk(cru, gclk_rate, periph);
}
-static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
+static ulong rockchip_spi_get_clk(struct rockchip_cru *cru, uint gclk_rate,
int periph)
{
uint div, mux;
@@ -681,7 +681,7 @@ static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
return DIV_TO_RATE(gclk_rate, div);
}
-static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
+static ulong rockchip_spi_set_clk(struct rockchip_cru *cru, uint gclk_rate,
int periph, uint freq)
{
int src_clk_div;
@@ -715,7 +715,7 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
return rockchip_spi_get_clk(cru, gclk_rate, periph);
}
-static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru)
+static ulong rockchip_saradc_get_clk(struct rockchip_cru *cru)
{
u32 div, val;
@@ -726,7 +726,7 @@ static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru)
return DIV_TO_RATE(OSC_HZ, div);
}
-static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz)
+static ulong rockchip_saradc_set_clk(struct rockchip_cru *cru, uint hz)
{
int src_clk_div;
@@ -785,7 +785,7 @@ static ulong rk3288_clk_get_rate(struct clk *clk)
static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
{
struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
- struct rk3288_cru *cru = priv->cru;
+ struct rockchip_cru *cru = priv->cru;
ulong new_rate, gclk_rate;
gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
@@ -892,7 +892,7 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
static int __maybe_unused rk3288_gmac_set_parent(struct clk *clk, struct clk *parent)
{
struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
- struct rk3288_cru *cru = priv->cru;
+ struct rockchip_cru *cru = priv->cru;
const char *clock_output_name;
int ret;
@@ -1008,15 +1008,15 @@ static int rk3288_clk_bind(struct udevice *dev)
debug("Warning: No sysreset driver: ret=%d\n", ret);
} else {
priv = malloc(sizeof(struct sysreset_reg));
- priv->glb_srst_fst_value = offsetof(struct rk3288_cru,
+ priv->glb_srst_fst_value = offsetof(struct rockchip_cru,
cru_glb_srst_fst_value);
- priv->glb_srst_snd_value = offsetof(struct rk3288_cru,
+ priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
cru_glb_srst_snd_value);
sys_child->priv = priv;
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
- ret = offsetof(struct rk3288_cru, cru_softrst_con[0]);
+ ret = offsetof(struct rockchip_cru, cru_softrst_con[0]);
ret = rockchip_reset_bind(dev, ret, 12);
if (ret)
debug("Warning: software reset driver bind faile\n");
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-23 08:51:09 +0300