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path: root/arch/arm/include/asm/arch-fsl-layerscape
AgeCommit message (Expand)AuthorFilesLines
2016-09-26Convert CONFIG_SYS_FSL_ERRATUM_A010315 to Kconfig optionYork Sun1-1/+0
2016-09-26armv8: ls1012a: Convert CONFIG_LS1012A to Kconfig option ARCH_LS1021AYork Sun2-5/+3
2016-09-26armv8: ls1046a: Convert CONFIG_LS1046A to Kconfig option ARCH_LS1046AYork Sun1-1/+2
2016-09-15armv8: ls1046a: Enable DDR erratum for ls1046aShengzhou Liu1-0/+6
2016-09-15armv8: fsl-layerscape: add define CONFIG_STANDALONE_LOAD_ADDR for standalone appShaohui Xie1-0/+2
2016-09-15driver/ddr/fsl: Add general MMDC driver and reuse common MMDC driver for ls1012aShengzhou Liu1-1/+3
2016-09-15armv8: ls2080a: Remove debug server supportYork Sun1-9/+0
2016-09-15fsl-layerscape: Add workaround for PCIe erratum A010315Hou Zhiqiang2-0/+6
2016-09-15fsl: csu: add an API to set R/W permission to PCIeHou Zhiqiang1-0/+1
2016-09-15fsl: serdes: ensure accessing the initialized maps of serdes protocolHou Zhiqiang1-0/+8
2016-08-27ARM: Move SYS_CACHELINE_SIZE over to KconfigTom Rini1-2/+0
2016-07-26armv8: fsl_lsch2: Add LS1046A SoC supportMingkai Hu4-1/+32
2016-07-26armv8: fsl_lsch2: Add SerDes 2 supportQianyu Gong2-0/+3
2016-07-26armv8: fsl-layerscape: Consolidate the LSCH2 common definesQianyu Gong1-39/+20
2016-07-26armv8: fsl-layerscape: Add A72 core detectionAlison Wang2-0/+2
2016-07-26include: usb: Rename USB controller base address mappingRajesh Bhagat2-5/+5
2016-07-19ARMv8/layerscape: Add FSL PPA supportHou Zhiqiang1-0/+16
2016-07-19armv8: layerscape: Convert to use common MMU frameworkYork Sun1-123/+187
2016-06-28armv8: fsl-layerscape: Append "A" in SoC name for ARM based SoCsPrabhakar Kushwaha2-14/+14
2016-06-19Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini3-0/+8
2016-06-13usb: xhci: fsl: Add workaround for USB erratum A008751Sriram Dash1-0/+1
2016-06-13arm64: fsl-layerscape: add get_svr and IS_SVR_REV helperSriram Dash3-0/+7
2016-06-10armv8: ls2080aqds: Enable QSPI boot supportYuan Yao1-0/+4
2016-06-10armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND bootYuan Yao1-0/+2
2016-06-10armv8: ls2080aqds: Select QSPI CLK div via SCFGYuan Yao1-0/+1
2016-06-10armv8/ls2080a: configure PMU's PCTBENR to enable WDTYunhui Cui1-0/+1
2016-06-04armv8: fsl-layerscape: Add support of QorIQ LS1012A SoCPrabhakar Kushwaha6-0/+46
2016-06-04armv8: fsl-layerscape: Avoid LS1043A specifc definesPrabhakar Kushwaha1-1/+1
2016-05-18driver/ddr/fsl: Add workaround for erratum A-010165Shengzhou Liu1-0/+1
2016-05-18arch/arm, arch/powerpc: add # of SEC engines on the SOCAlex Porosanu1-0/+2
2016-05-18arch/arm: add SEC JR0 offsetAlex Porosanu2-4/+13
2016-05-17driver/ddr/fsl: Add workaround for erratum A-009801Shengzhou Liu1-0/+1
2016-05-17armv8/ls1043: Add workaround for DDR erratum A-008850Shengzhou Liu1-0/+1
2016-04-06armv8: LS2080A: Consolidate LS2080A and LS2085AYork Sun4-9/+7
2016-04-06armv8: LSCH2 early and final mmu needs matching NS attributeEd Swarthout1-4/+8
2016-03-29armv8/ls2080ardb: Enable VID supportRai Harninder1-0/+4
2016-03-29armv8: fsl-layerscape: Add LS1023A SVRMingkai Hu2-0/+2
2016-03-29armv8: fsl-layerscape: Fix LS1043A SVR registerMingkai Hu1-1/+1
2016-03-29armv8: fsl-lsch3: Disable SMMU during secure bootSaksham Jain1-0/+15
2016-03-29armv8: ls2080: Add config for endianess of CCSR GURSaksham Jain1-0/+3
2016-03-29armv8: fsl-lsch3: Add new header for secure bootSaksham Jain1-1/+2
2016-03-29armv8: ls2080: Add configs for SEC, SecMon, SRK and DCFGSaksham Jain2-0/+20
2016-03-29armv8: ls2080: Add SFP Configs for LS2080Saksham Jain2-0/+7
2016-03-21driver/ddr/fsl: Add workaround for erratum A-009803Shengzhou Liu1-0/+1
2016-03-21pci/layerscape: add defines for LUTStuart Yoder1-0/+4
2016-03-21armv8: ls2080a: update stream ID partitioning infoStuart Yoder1-21/+34
2016-03-21armv8: ls2080ardb: invert irq pins polarity for AQR405 PHYShaohui Xie1-0/+4
2016-03-21armv8: lsch3: Enable WUO config for RNI-20 nodePrabhakar Kushwaha1-0/+2
2016-03-15arm64: Remove non-full-va map codeAlexander Graf1-47/+47
2016-02-24armv8/ls1043a: Implement workaround for erratum A009660Mingkai Hu1-0/+1
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