summaryrefslogtreecommitdiff
path: root/arch/arm/include/asm/arch-socfpga
AgeCommit message (Expand)AuthorFilesLines
2015-05-07ARM: socfpga: move SoC headers to mach-socfpga/include/machMasahiro Yamada13-1061/+0
2015-04-21arm: socfpga: spl: Add stub sdram.hMarek Vasut1-0/+19
2015-04-21arm: socfpga: spl: allow bootrom to enable IOs after warm resetDinh Nguyen1-0/+1
2015-04-21arm: socfpga: add functions to bring sdram, timer, and uart out of resetDinh Nguyen1-0/+6
2014-12-06socfpga: correctly increment freeze_controller_base addressDinh Nguyen1-1/+0
2014-12-06socfpga: add missing struct member fifo_triple_byteDinh Nguyen1-0/+1
2014-12-06arm: socfpga: Add missing DW master SPI clock prototyp to clock_manager.hStefan Roese1-0/+1
2014-11-07arm: socfpga: Add socfpga_spim_enable() to reset_manager.cStefan Roese1-0/+3
2014-11-07arm: socfpga: Add DT support for SoCFPGA and add socfpga_socrates targetStefan Roese1-0/+10
2014-10-27arm: socfpga: Zap spl.h and ad-hoc related symsMarek Vasut1-15/+0
2014-10-06arm: socfpga: nic301: Add NIC-301 GPV register fileMarek Vasut1-0/+195
2014-10-06arm: socfpga: scu: Add SCU register fileMarek Vasut1-0/+23
2014-10-06arm: socfpga: reset: Add function to reset FPGA bridgesMarek Vasut1-0/+2
2014-10-06arm: socfpga: fpga: Add SoCFPGA FPGA programming interfacePavel Machek1-0/+77
2014-10-06arm: socfpga: misc: Add proper ethernet initializationPavel Machek1-0/+9
2014-10-06arm: socfpga: reset: Add EMAC reset functionsMarek Vasut1-0/+3
2014-10-06arm: socfpga: clock: Sync with reference codeMarek Vasut1-0/+3
2014-10-06arm: socfpga: clock: Clean up bit definitionsMarek Vasut1-154/+176
2014-10-06arm: socfpga: clock: Add code to read clock configurationPavel Machek1-2/+41
2014-10-06arm: socfpga: clock: Implant order into bit definitionsMarek Vasut1-67/+99
2014-10-06arm: socfpga: sysmgr: Clean up system managerMarek Vasut1-26/+76
2014-10-06arm: socfpga: Add watchdog disable for socfpgaPavel Machek1-0/+4
2014-10-06arm: socfpga: Clean up base address fileMarek Vasut1-51/+51
2014-10-06arm: socfpga: Complete the list of base addressesPavel Machek1-0/+40
2014-08-30socfpga: initialize designware ethernetPavel Machek1-0/+2
2014-08-29socfpga: Fix SOCFPGA build error for Altera dev kitChin Liang See1-0/+2
2014-08-29socfpga: fix clock manager register definitionPavel Machek1-43/+49
2014-07-05socfpga: Adding Scan Manager driverChin Liang See2-0/+91
2014-07-05socfpga: Adding DesignWare watchdog supportChin Liang See1-0/+1
2014-04-07socfpga: Adding Clock Manager driverChin Liang See2-0/+206
2014-01-09socfpga/dwmmc: Adding DesignWare MMC driver support for SOCFPGAChin Liang See2-0/+77
2013-12-03socfpga: Adding Freeze Controller driverChin Liang See1-0/+50
2013-10-07socfpga: Adding System Manager driverChin Liang See2-0/+23
2013-09-06socfpga: Creating driver for Reset ManagerChin Liang See1-3/+7
2013-07-24Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk4-48/+4
2012-10-04ARM: Add Altera SOCFPGA Cyclone5Dinh Nguyen4-0/+119
generated by cgit v1.2.3 (git 2.39.0) at 2024-08-11 00:48:04 +0300