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path: root/arch/arm/mach-tegra/tegra210/clock.c
AgeCommit message (Expand)AuthorFilesLines
2023-02-23ARM: tegra: Fix Tegra PWM parent clockSvyatoslav Ryhel1-1/+1
2023-02-23ARM: tegra: clock: add clk_id_to_pll_id helperSvyatoslav Ryhel1-0/+37
2023-02-02ARM: tegra: remap clock_osc_freq for all Tegra familySvyatoslav Ryhel1-18/+4
2022-01-19doc: replace @return by Return:Heinrich Schuchardt1-2/+2
2020-05-19common: Drop linux/bitops.h from common headerSimon Glass1-0/+1
2020-05-19common: Drop linux/delay.h from common headerSimon Glass1-0/+1
2020-05-19common: Drop log.h from common headerSimon Glass1-0/+1
2020-05-19common: Drop init.h from common headerSimon Glass1-0/+1
2020-05-19common: Drop net.h from common headerSimon Glass1-0/+1
2020-04-03i2c: t210: Add VI_I2C clock source supportTom Warren1-4/+4
2020-04-03t210: do not enable PLLE and UPHY PLL HW PWRSEQJC Kuo1-19/+0
2019-06-05ARM: tegra: Remove disp1 clock initialization on Tegra210Thierry Reding1-1/+0
2019-06-05ARM: tegra: Fix mux type for disp1 and disp2 clocks on Tegra210Thierry Reding1-5/+5
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini1-2/+1
2016-09-27ARM: tegra: add APIs the clock uclass driver will needStephen Warren1-16/+48
2016-09-27ARM: tegra: add peripheral clock init tableStephen Warren1-0/+23
2016-03-29ARM: tegra210: set PLLE_PTS bit when enabling PLLEStephen Warren1-0/+2
2015-11-12ARM: tegra210: implement PLLE init procedure from TRMStephen Warren1-47/+132
2015-09-17ARM: tegra: clk_m is the architected timer source clockThierry Reding1-6/+4
2015-09-17ARM: tegra: Implement clk_mThierry Reding1-0/+11
2015-08-13tegra: Correct logic for reading pll_misc in clock_start_pll()Simon Glass1-0/+7
2015-08-06Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.Tom Warren1-1/+30
2015-08-06Tegra: clocks: Add 38.4MHz OSC support for T210 useTom Warren1-2/+6
2015-07-28ARM: Tegra210: Add SoC code/include files for T210Tom Warren1-0/+1091