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Fedora_JH7100_2021.07
Fedora_JH7100_upstream
Fedora_JH7100_upstream_devel
JH7100_Multimedia_V0.1.0
JH7100_VisionFive_OH_dev
JH7100_VisionFive_devel
JH7100_starlight_multimedia
JH7100_upstream
JH7100_upstream_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_devel-v3.9.3
dubhe_fpga_dev_v2023.10
master
rtthread_AMP
visionfive_devel
StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
arch
/
arm
/
mach-tegra
/
tegra210
/
clock.c
Age
Commit message (
Expand
)
Author
Files
Lines
2023-02-23
ARM: tegra: Fix Tegra PWM parent clock
Svyatoslav Ryhel
1
-1
/
+1
2023-02-23
ARM: tegra: clock: add clk_id_to_pll_id helper
Svyatoslav Ryhel
1
-0
/
+37
2023-02-02
ARM: tegra: remap clock_osc_freq for all Tegra family
Svyatoslav Ryhel
1
-18
/
+4
2022-01-19
doc: replace @return by Return:
Heinrich Schuchardt
1
-2
/
+2
2020-05-19
common: Drop linux/bitops.h from common header
Simon Glass
1
-0
/
+1
2020-05-19
common: Drop linux/delay.h from common header
Simon Glass
1
-0
/
+1
2020-05-19
common: Drop log.h from common header
Simon Glass
1
-0
/
+1
2020-05-19
common: Drop init.h from common header
Simon Glass
1
-0
/
+1
2020-05-19
common: Drop net.h from common header
Simon Glass
1
-0
/
+1
2020-04-03
i2c: t210: Add VI_I2C clock source support
Tom Warren
1
-4
/
+4
2020-04-03
t210: do not enable PLLE and UPHY PLL HW PWRSEQ
JC Kuo
1
-19
/
+0
2019-06-05
ARM: tegra: Remove disp1 clock initialization on Tegra210
Thierry Reding
1
-1
/
+0
2019-06-05
ARM: tegra: Fix mux type for disp1 and disp2 clocks on Tegra210
Thierry Reding
1
-5
/
+5
2018-05-07
SPDX: Convert all of our single license tags to Linux Kernel style
Tom Rini
1
-2
/
+1
2016-09-27
ARM: tegra: add APIs the clock uclass driver will need
Stephen Warren
1
-16
/
+48
2016-09-27
ARM: tegra: add peripheral clock init table
Stephen Warren
1
-0
/
+23
2016-03-29
ARM: tegra210: set PLLE_PTS bit when enabling PLLE
Stephen Warren
1
-0
/
+2
2015-11-12
ARM: tegra210: implement PLLE init procedure from TRM
Stephen Warren
1
-47
/
+132
2015-09-17
ARM: tegra: clk_m is the architected timer source clock
Thierry Reding
1
-6
/
+4
2015-09-17
ARM: tegra: Implement clk_m
Thierry Reding
1
-0
/
+11
2015-08-13
tegra: Correct logic for reading pll_misc in clock_start_pll()
Simon Glass
1
-0
/
+7
2015-08-06
Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.
Tom Warren
1
-1
/
+30
2015-08-06
Tegra: clocks: Add 38.4MHz OSC support for T210 use
Tom Warren
1
-2
/
+6
2015-07-28
ARM: Tegra210: Add SoC code/include files for T210
Tom Warren
1
-0
/
+1091