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starfive-tech/u-boot.git
Fedora_JH7100_2021.04
Fedora_JH7100_2021.07
Fedora_JH7100_upstream
Fedora_JH7100_upstream_devel
JH7100_Multimedia_V0.1.0
JH7100_VisionFive_OH_dev
JH7100_VisionFive_devel
JH7100_starlight_multimedia
JH7100_upstream
JH7100_upstream_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_devel-v3.9.3
dubhe_fpga_dev_v2023.10
master
rtthread_AMP
visionfive_devel
StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
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path:
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arch
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arm
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mach-tegra
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tegra210
Age
Commit message (
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Author
Files
Lines
2020-05-19
common: Drop linux/delay.h from common header
Simon Glass
2
-0
/
+2
2020-05-19
common: Drop log.h from common header
Simon Glass
3
-0
/
+3
2020-05-19
common: Drop init.h from common header
Simon Glass
1
-0
/
+1
2020-05-19
common: Drop net.h from common header
Simon Glass
1
-0
/
+1
2020-04-03
ARM: tegra: Add NVIDIA Jetson Nano Developer Kit support
Tom Warren
1
-0
/
+7
2020-04-03
i2c: t210: Add VI_I2C clock source support
Tom Warren
1
-4
/
+4
2020-04-03
t210: pinmux: Remove pinmux/GPIO init from T210 boards
Tom Warren
2
-196
/
+1
2020-04-03
t210: do not enable PLLE and UPHY PLL HW PWRSEQ
JC Kuo
2
-44
/
+43
2019-07-10
arm64: add an option to switch visibility of CONFIG_SYS_INIT_SP_BSS_OFFSET
Masahiro Yamada
1
-3
/
+0
2019-06-05
ARM: tegra: Remove disp1 clock initialization on Tegra210
Thierry Reding
1
-1
/
+0
2019-06-05
ARM: tegra: Fix mux type for disp1 and disp2 clocks on Tegra210
Thierry Reding
1
-5
/
+5
2018-05-07
SPDX: Convert all of our single license tags to Linux Kernel style
Tom Rini
4
-8
/
+4
2018-01-12
ARM: tegra: use CONFIG_SYS_INIT_SP_BSS_OFFSET
Stephen Warren
1
-0
/
+3
2017-10-04
treewide: replace with error() with pr_err()
Masahiro Yamada
1
-1
/
+1
2017-07-28
dm: tegra: Convert USB setup to livetree
Simon Glass
1
-11
/
+31
2017-01-24
Kconfig: Migrate BOARD_LATE_INIT to a select
Tom Rini
1
-0
/
+4
2016-09-27
ARM: tegra: add APIs the clock uclass driver will need
Stephen Warren
1
-16
/
+48
2016-09-27
ARM: tegra: add peripheral clock init table
Stephen Warren
1
-0
/
+23
2016-03-29
ARM: tegra210: set PLLE_PTS bit when enabling PLLE
Stephen Warren
1
-0
/
+2
2015-11-12
ARM: tegra: note that p2371-2180 is Jetson TX1
Stephen Warren
1
-5
/
+5
2015-11-12
ARM: tegra: error check Tegra210 XUSB padctl waits
Stephen Warren
1
-5
/
+20
2015-11-12
ARM: tegra: add lane tables to Tegra210 XUSB padctl
Stephen Warren
1
-4
/
+74
2015-11-12
ARM: tegra: switch Tegra210 to common XUSB padctl
Stephen Warren
2
-158
/
+16
2015-11-12
ARM: tegra210: implement PLLE init procedure from TRM
Stephen Warren
1
-47
/
+132
2015-09-17
ARM: tegra: clk_m is the architected timer source clock
Thierry Reding
1
-6
/
+4
2015-09-17
ARM: tegra: Implement clk_m
Thierry Reding
1
-0
/
+11
2015-09-17
ARM: tegra: Add p2371-2180 board
Stephen Warren
1
-0
/
+9
2015-08-13
tegra: Correct logic for reading pll_misc in clock_start_pll()
Simon Glass
1
-0
/
+7
2015-08-06
ARM: tegra: Add p2371-0000 board
Stephen Warren
1
-0
/
+9
2015-08-06
ARM: tegra: Add e2220-1170 board
Stephen Warren
1
-0
/
+8
2015-08-06
Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.
Tom Warren
1
-1
/
+30
2015-08-06
Tegra: clocks: Add 38.4MHz OSC support for T210 use
Tom Warren
1
-2
/
+6
2015-07-28
T210: Add support for 64-bit T210-based P2571 board
Tom Warren
1
-0
/
+7
2015-07-28
ARM: Tegra210: Add SoC code/include files for T210
Tom Warren
5
-0
/
+1648
2015-03-30
ARM: tegra: pinctrl: move Tegra210 code to the correct dir
Stephen Warren
1
-0
/
+195