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2023-02-28arm64: dts: rockchip: rk3308: Add Radxa ROCK Pi S supportAkash Gajjar2-0/+245
Add Radxa ROCK 3 Model A support. sync rk3308-rock-pi-s.dts from Linux 6.2.0-rc7. ROCK Pi S is RK3308 based SBC from radxa.com. ROCK Pi S has a, - 256MB/512MB DDR3 RAM - SD, NAND flash (optional on board 1/2/4/8Gb) - 100MB ethernet, PoE (optional) - Onboard 802.11 b/g/n wifi + Bluetooth 4.0 Module - USB2.0 Type-A HOST x1 - USB3.0 Type-C OTG x1 - 26-pin expansion header - USB Type-C DC 5V Power Supply Linux commit commit for the same, <2e04c25b1320> ("arm64: dts: rockchip: add ROCK Pi S DTS support") Signed-off-by: Akash Gajjar <gajjar04akash@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28arm64: dts: rockchip: rk3568: Add Radxa ROCK 3 Model A board supportAkash Gajjar3-1/+635
Add Radxa ROCK 3 Model A support. sync rk3568-rock-3a.dts from Linux 6.2.0-rc7 Board Specifications - Rockchip RK3568 - 2/4/8GB LPDDR4 3200MT/s - eMMC socket, SD card slot - GbE LAN - PCIe 3.0/2.0 - M.2 Connector - 3.5mm Audio jack with mic - HDMI 2.0, MIPI DSI/CSI - USB 3.0 Host/OTG, USB 2.0 Host - 40-pin GPIO expansion ports - USB Type C PD 2.0, 9V/2A, 12V/2A, 15V/2A, 20V/2A Refer Linux commit <22a442e6586c> ("arm64: dts: rockchip: add basic dts for the radxa rock3 model a") Signed-off-by: Akash Gajjar <gajjar04akash@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: Use an external TPL binary on RK3568Jonas Karlman2-2/+16
Rockchip SoCs typically use U-Boot TPL to initialize DRAM, then jumps back to BootRom to load next stage, U-Boot SPL, into DRAM. BootRom then jumps to U-Boot SPL to continue the normal boot flow. However, there is no support to initialize DRAM on RK35xx SoCs using U-Boot TPL and instead an external TPL binary must be used to generate a bootable u-boot-rockchip.bin image. Add CONFIG_ROCKCHIP_EXTERNAL_TPL to indicate that an external TPL should be used. Build U-Boot with ROCKCHIP_TPL=/path/to/ddr.bin to generate a bootable u-boot-rockchip.bin image for RK3568. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-02-28rockchip: dts: rk3328: fix sdram paramsJonas Karlman4-0/+40
The rk3328 sdram driver read sdram parameters from the devicetree into a struct rk3328_sdram_params using dev_read_u32_array. After commit 5ab30c3176bf ("ram: rockchip: Update ddr pctl regs for px30") changed the size of struct ddr_pctl_regs, a member of struct rk3328_sdram_params, U-Boot TPL can no longer initialize DRAM on RK3328. Add ten u32 to the sdram parameter array in devicetree to align with this size change. This fixes DRAM initialization on RK3328. Fixes: 5ab30c3176bf ("ram: rockchip: Update ddr pctl regs for px30") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # roc-rk3328-cc
2023-02-28rockchip: sdram: add dram bank with usable memory beyond 4GBJonas Karlman1-3/+9
Add a second dram bank of usable memory beyond the blob of space for peripheral near 4GB. Any memory that exists beyond the 4GB mark is added to the second bank. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: sdram: add basic support for sdram reg info version 3Jonas Karlman2-11/+26
Newer DRAM initialization blobs from vendor can encode sdram info in a new version 3 format. The new format makes use of more bits in sys_reg3 compared to the version 2 format. Add basic support for detecting the version 3 format and decoding the high bits used for ddrtype. This fixes decode of sdram size on my RK3568 boards that have LPDDR4X. Details on the new format was deciphered from vendor u-boot commit [1]. [1] https://github.com/rockchip-linux/u-boot/commit/c69667e0e2bf4290ab1f408fcde58b8806ac266b Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28arm: dts: rockchip: rk3399: nanopi-r4s: Provide smbios sysinfoChristian Kohlschütter1-0/+22
Provide human-readable manufacturer and product names for the FriendlyELEC NanoPi R4S. Enable CONFIG_SYSINFO and CONFIG_SYSINFO_SMBIOS by default. Signed-off-by: Christian Kohlschütter <christian@kohlschutter.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-23ARM: tegra20: implement BCT patchingSvyatoslav Ryhel4-4/+124
This function allows updating bootloader from u-boot on production devices without need in host PC. Be aware! It works only with re-crypt BCT. Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Signed-off-by: Ramin Khonsari <raminterex@yahoo.com> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra30: implement BCT patchingRamin Khonsari4-0/+131
This function allows updating bootloader from u-boot on production devices without need in host PC. Be aware! It works only with re-crypted BCT. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Signed-off-by: Ramin Khonsari <raminterex@yahoo.com> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra: crypto: extend crypto functionalSvyatoslav Ryhel3-38/+91
Add support for encryption, decryption and signinig with non-zero key saving backward compatibility. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra: expose crypto module for all Tegra SoCsSvyatoslav Ryhel6-1/+8
Move crypto module from T20 only into common Tegra dir. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23board: tegra30: switch to updated pre-dm i2c writeSvyatoslav Ryhel2-44/+0
Configure PMIC voltages for early stages using updated early i2c write. Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra: create common pre-dm i2c writeSvyatoslav Ryhel4-26/+33
This implementation allows pwr i2c writing on early SPL stages when DM is not yet setup. Such writing is needed to configure main voltages of PMIC on early SPL for bootloader to boot properly. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra: add late init supportSvyatoslav Ryhel2-0/+8
Late init function allows passing values like identifiers and perform device specific configurations of pre-boot stage. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra: Fix Tegra PWM parent clockSvyatoslav Ryhel7-7/+7
Default parent clock for the PWM on Tegra is a 32kHz clock and is unable to support the requested PWM period. Fix PWM support on Tegra20, Tegra30, Tegra114, Tegra124 and Tegra210 by updating the parent clock for the PWM to be the PLL_P. This commit is equivalent to Linux kernel commit: https://lore.kernel.org/all/20221010100046.6477-1-jonathanh@nvidia.com/ Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # ASUS TF201 T30 Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra30: add PLLD to pll setupSvyatoslav Ryhel1-0/+41
On T30 unlike T20 dsi panels are wider used on devices and PLLD is used as DISP1 parent more often, so lets enable it as well for this cases. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF700T T30 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X T30 Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra: clock: add clock_decode_pair helperSvyatoslav Ryhel2-0/+36
Get periph clock id and its parent from device tree. This works by looking up the peripheral's 'clocks' node and reading out the second and fourth cells, which are the peripheral and PLL clock numbers. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra: clock: add clk_id_to_pll_id helperSvyatoslav Ryhel6-0/+194
This function allows to convert a device tree clock ID to PLL ID. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: t20/t30: swap host1x and disp1 clock parentsSvyatoslav Ryhel2-4/+4
According to mainline clock tables and TRM HOST1X parent is PLLC, while DISP1 usually uses PLLP as parent clock. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23tegra30: clock: add EXTPERIPHSvyatoslav Ryhel2-6/+6
This mappings were missing for some reason. Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-22arm: dts: chameleonv3: Add 270-2 variantPaweł Anikiel3-0/+18
Add devicetree for chameleonv3 with the 270-2I2-D11E variant of the Mercury+ AA1 module Signed-off-by: Paweł Anikiel <pan@semihalf.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-22arm: dts: chameleonv3: Rename chameleonv3.dts to .dtsiPaweł Anikiel3-2/+2
This file is included by the different chameleonv3 variants. Change the name to .dtsi. Signed-off-by: Paweł Anikiel <pan@semihalf.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-22arm: dts: chameleonv3: Override chameleonv3 bitstream namesPaweł Anikiel2-0/+8
Set the bitstream name per Chameleon variant. This allows the same boot filesystem with all bitstream variants to be used on different boards. Signed-off-by: Paweł Anikiel <pan@semihalf.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-13clocks: qcs404: Add support for I2C clocksSumit Garg2-0/+75
Co-developed-by: Mike Worsfold <mworsfold@impinj.com> Signed-off-by: Mike Worsfold <mworsfold@impinj.com> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2023-02-13Merge tag 'i2c-updates-for-v2023.04' of ↵Tom Rini1-0/+1
https://source.denx.de/u-boot/custodians/u-boot-i2c i2c updates for v2023.04 - add new i2c driver ast2600 from Ryan Chen - i2c-cdns: make read fifo-depth configurable through device tree from Pei Yue Ho - mxc i2c driver: print base address in hex, not in decimal from Fabio
2023-02-13arm: kirkwood: Enable uart0 dm-pre-reloc for Pogoplug V4 boardTony Dinh1-0/+7
When DM_SERIAL is enabled, the device-tree tag u-boot,dm-pre-reloc is required for this board to boot over UART with kwboot. Enable this in kirkwood-pogoplug-series-4-u-boot.dtsi. Added by Stefan while applying: Please note that it's not fully understood, why this property really is needed. Here a link to the discussion about this: https://lore.kernel.org/r/20230201080210.ypz4nrj4y2igwxz3@pali/ Signed-off-by: Tony Dinh <mibodhi@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2023-02-13arm: mvebu: Add support for Synology DS116 (Armada 385)Tony Dinh3-0/+299
Synology DS116 is a NAS based on Marvell Armada 385 SoC. Board Specification: - Marvel MV88F6820 Dual Core at 1.8GHz - 1 GiB DDR3 RAM - 8MB Macronix mx25l6405d SPI flash - I2C - 2x USB 3.0 - 1x GBE LAN port (PHY: Marvell 88E1510) - 1x SATA (6 Gbps) - 3x LED - PIC16F1829 (connected to uart1) - GPIO fan - serial console Note that this patch depends on the add-support for Thecus N2350 patch: https://patchwork.ozlabs.org/project/uboot/patch/20230201231306.7010-1-mibodhi@gmail.com/ Signed-off-by: Tony Dinh <mibodhi@gmail.com>
2023-02-13arm: mvebu: Add support for Thecus N2350 (Armada 385) boardTony Dinh3-0/+458
Thecus N2350 is a NAS based on Marvell Armada 385 SoC. Specification: - Processor: Marvel MV88F6820 Dual Core at 1GHz - 1 GiB DDR4 RAM - 4MB Macronix mx25l3205d SPI flash - 512MB Hynix H27U4G8F2DTR-BC NAND flash - I2C - 2x USB 3.0 - 1x GBE LAN port (PHY: Marvell 88E1510) - 2x SATA (hot swap slots) - 3x buttons - 10x LEDS - serial console Signed-off-by: Tony Dinh <mibodhi@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2023-02-13arm: kirkwood: Use CONFIG_SYS_NS16550 with DM_SERIAL for Kirkwood boardsTony Dinh1-0/+1
CONFIG_SYS_NS16550 is required when DM_SERIAL is enabled for Kirkwood boards. Signed-off-by: Tony Dinh <mibodhi@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefan Roese <sr@denx.de>
2023-02-13arm: aspeed: dtsi: add reg for i2cRyan Chen1-0/+1
The i2c driver have global register that i2c bus use ofnode_get_parent to get parent register address. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2023-02-12socfpga: fix the serial console on DE1-SoCJade Lovelace1-0/+1
Previously, the TX LED would flash but nothing would appear on the serial port, and the board would appear dead with a build of the socfpga_cyclone5_defconfig. I have verified that adding the frequency to the uart will fix the serial console on my board. Thanks to @ehoffman on the Rocketboards forum: https://forum.rocketboards.org/t/cyclonev-programming-fpga-from-u-boot/2230/30 Signed-off-by: Jade Lovelace <lists@jade.fyi> Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-10dts: add missing linux,code in gpio-keysDzmitry Sankouski4-2/+6
gpio-keys linux driver enforces user to specify linux,code. Add missing linux,code before implementing button input support. - arch/arm/dts/rk3288-popmetal.dtsi -> KEY_POWER - arch/arm/dts/rk3288-tinker.dtsi -> KEY_POWER - arch/arm/dts/am3517-evm-ui.dtsi -> KEY_RECORD - sandbox/dts/sandbox.dtsi -> BTN_1 - sandbox/dts/sandbox.dts -> BTN_1 Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-10dts: qcs404-evb: Add I2C controller nodesSumit Garg1-0/+97
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2023-02-10pinctrl: qcs404: Enable I2C pinmux optionsSumit Garg1-0/+6
Co-developed-by: Mike Worsfold <mworsfold@impinj.com> Signed-off-by: Mike Worsfold <mworsfold@impinj.com> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2023-02-10clock-snapdragon: Add clk_rcg_set_rate() with mnd_width=0Sumit Garg2-0/+26
Add clk_rcg_set_rate() which allows to configure clocks without programming MND values. This is required for configuring I2C clocks on QCS404. Co-developed-by: Mike Worsfold <mworsfold@impinj.com> Signed-off-by: Mike Worsfold <mworsfold@impinj.com> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2023-02-10dts: qcs404-evb: Add ethernet controller nodeSumit Garg1-1/+97
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2023-02-10pinctrl-snapdragon: Get rid of custom drive-strength valuesSumit Garg5-7/+9
Use standard pinconf drive-strength values from Linux DT bindings rather than ones based on custom u-boot header. These changes are in direction to make u-boot DTs for Qcom SoCs to be compatible with standard Linux DT bindings. Also, add support for pinconf bias-pull-up. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2023-02-10pinctrl: qcs404: Enable ethernet pinmux optionsSumit Garg1-0/+7
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2023-02-10clocks: qcs404: Add support for ethernet clocksSumit Garg2-0/+74
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2023-02-10qcs404-evb: Enable msm_gpio driver supportSumit Garg1-0/+4
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2023-02-10qcs404: sysmap: Don't map reserved memory rangesSumit Garg1-1/+13
Currently u-boot maps whole of 1G RAM but there reserved memory ranges on QCS404 which are reserved for TrustZone, various firmware components etc. Any access to these reserved memory ranges causes a bus hang issue. So disable mapping for reserved memory ranges in u-boot. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2023-02-10Correct SPL uses of ROCKCHIP_OTPSimon Glass1-2/+2
This converts 2 usages of this option to the non-SPL form, since there is no SPL_ROCKCHIP_OTP defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10Correct SPL uses of FASTBOOTSimon Glass1-1/+1
This converts 3 usages of this option to the non-SPL form, since there is no SPL_FASTBOOT defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10Correct SPL use of SYS_FSL_ERRATUM_A010539Simon Glass1-1/+1
This converts 1 usage of this option to the non-SPL form, since there is no SPL_SYS_FSL_ERRATUM_A010539 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10Correct SPL use of STM32MP15X_STM32IMAGESimon Glass1-1/+1
This converts 1 usage of this option to the non-SPL form, since there is no SPL_STM32MP15X_STM32IMAGE defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10Correct SPL uses of SAVE_PREV_BL_INITRAMFS_START_ADDRSimon Glass1-1/+1
This converts 2 usages of this option to the non-SPL form, since there is no SPL_SAVE_PREV_BL_INITRAMFS_START_ADDR defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10Correct SPL uses of SAVE_PREV_BL_FDT_ADDRSimon Glass1-1/+1
This converts 2 usages of this option to the non-SPL form, since there is no SPL_SAVE_PREV_BL_FDT_ADDR defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10Correct SPL uses of ROCKCHIP_EFUSESimon Glass1-2/+2
This converts 2 usages of this option to the non-SPL form, since there is no SPL_ROCKCHIP_EFUSE defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10Correct SPL uses of PMIC_STPMIC1Simon Glass1-2/+2
This converts 2 usages of this option to the non-SPL form, since there is no SPL_PMIC_STPMIC1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10Correct SPL uses of MTDSimon Glass1-1/+1
This converts 2 usages of this option to the non-SPL form, since there is no SPL_MTD defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.2.3 (git 2.39.0) at 2024-10-12 18:30:29 +0300