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starfive-tech/u-boot.git
Fedora_JH7100_2021.04
Fedora_JH7100_2021.07
Fedora_JH7100_upstream
Fedora_JH7100_upstream_devel
JH7100_Multimedia_V0.1.0
JH7100_VisionFive_OH_dev
JH7100_VisionFive_devel
JH7100_starlight_multimedia
JH7100_upstream
JH7100_upstream_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_devel-v3.9.3
dubhe_fpga_dev_v2023.10
master
rtthread_AMP
visionfive_devel
StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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arch
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riscv
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cpu
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ax25
Age
Commit message (
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Author
Files
Lines
2023-02-17
riscv: Rename Andes cpu and board names
Leo Yu-Chi Liang
5
-230
/
+0
2023-02-17
configs: ae350: Enable v5l2 cache for AE350 platforms in SPL
Yu Chien Peter Lin
1
-0
/
+1
2023-02-17
riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL
Yu Chien Peter Lin
1
-30
/
+68
2023-02-17
riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()
Yu Chien Peter Lin
1
-37
/
+12
2023-02-17
riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"
Leo Yu-Chi Liang
2
-92
/
+2
2023-02-01
riscv: ax25: bypass malloc when spl fit boots from ram
Rick Chen
2
-0
/
+28
2023-02-01
riscv: ae350: Enable CCTL_SUEN
Rick Chen
1
-7
/
+11
2022-11-03
riscv: Rename Andes PLIC to PLICSW
Yu Chien Peter Lin
1
-1
/
+1
2021-10-07
riscv: ae350: enable Coherence Manager for ae350
Leo Yu-Chi Liang
1
-0
/
+42
2021-03-27
cpu: Rename SPL_CPU_SUPPORT to SPL_CPU
Simon Glass
1
-1
/
+1
2020-10-26
timer: Add _TIMER suffix to Andes PLMT Kconfig
Sean Anderson
1
-1
/
+1
2020-09-30
riscv: Rework riscv timer driver to only support S-mode
Sean Anderson
1
-1
/
+1
2020-05-19
common: Drop net.h from common header
Simon Glass
1
-0
/
+1
2020-04-23
riscv: ax25: cache: Remove SPL_RISCV_MMODE config check
Pragnesh Patel
1
-8
/
+8
2019-12-10
riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL
Rick Chen
1
-14
/
+46
2019-12-10
riscv: ax25: add SPL support
Rick Chen
1
-1
/
+3
2019-12-03
common: Move ARM cache operations out of common.h
Simon Glass
1
-0
/
+1
2019-12-03
common: Move some cache and MMU functions out of common.h
Simon Glass
2
-0
/
+2
2019-09-03
riscv: cache: use CCTL to flush d-cache
Rick Chen
1
-9
/
+13
2019-09-03
riscv: cache: Flush L2 cache before jump to linux
Rick Chen
1
-0
/
+17
2019-09-03
riscv: ax25: add imply v5l2 cache controller
Rick Chen
1
-0
/
+1
2019-08-26
riscv: add run mode configuration for SPL
Lukas Auer
1
-3
/
+3
2019-05-18
CONFIG_SPL_SYS_[DI]CACHE_OFF: add
Trevor Woerner
1
-4
/
+4
2019-04-08
riscv: ax25: Andes specific cache shall only support in M-mode
Rick Chen
1
-0
/
+1
2019-04-08
riscv: ax25: Add platform-specific Kconfig options
Rick Chen
1
-0
/
+6
2019-01-15
riscv: move the AX25-specific implementation of flush_dcache_all
Lukas Auer
1
-0
/
+22
2018-12-18
riscv: ax25: Hide the ax25-specific Kconfig option
Bin Meng
2
-11
/
+18
2018-11-26
riscv: cache: Implement i/dcache [status, enable, disable]
Rick Chen
4
-0
/
+107
2018-10-03
riscv: Move do_reset() to a common place
Bin Meng
1
-9
/
+0
2018-10-03
riscv: Make start.S available for all targets
Bin Meng
2
-294
/
+0
2018-10-03
riscv: Move the linker script to the CPU root directory
Bin Meng
1
-90
/
+0
2018-08-20
riscv: Include bss subsections in linker script
Alexander Graf
1
-1
/
+1
2018-07-25
efi_loader: Rename sections to allow for implicit data
Alexander Graf
1
-10
/
+16
2018-05-29
riscv: cpu: nx25: Rename as ax25
Rick Chen
4
-0
/
+416