starfive-tech/u-boot.git - StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2023-08-10	riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation	Shengyu Qu	1	-0/+12
2023-07-24	riscv: setup per-hart stack earlier	Bo Gan	1	-13/+24
2023-04-20	riscv: spl: Remove relocation sections	Bin Meng	1	-0/+2
2023-04-20	riscv: Avoid updating the link register	Bin Meng	1	-1/+1
2023-04-20	riscv: Change to use positive offset to access relocation entries	Bin Meng	1	-12/+7
2023-04-20	riscv: Optimize loading relocation type	Bin Meng	1	-1/+0
2023-04-20	riscv: Optimize source end address calculation in start.S	Bin Meng	1	-3/+1
2022-09-26	riscv: Introduce AVAILABLE_HARTS	Rick Chen	1	-5/+8
2022-09-26	spl: introduce SPL_XIP to config	Nikita Shubin	1	-2/+2
2022-08-11	riscv: ae350: Fix XIP config boot failure	Leo Yu-Chi Liang	1	-1/+3
2022-08-11	riscv: cpu: set gp before board_init_f_init_reserve	Nikita Shubin	1	-0/+1
2022-06-06	Migrate CUSTOM_SYS_INIT_SP_ADDR to Kconfig using system-constants.h	Tom Rini	1	-1/+2
2021-10-18	riscv: Remove OF_PRIOR_STAGE from RISC-V boards	Ilias Apalodimas	1	-5/+0
2021-05-05	riscv: cpu: Add callback to init each core	Green Wan	1	-0/+4
2020-12-14	riscv: fix the wrong swap value register	Brad Kim	1	-1/+1
2020-09-30	riscv: Add some comments to start.S	Sean Anderson	1	-2/+17
2020-09-30	riscv: Ensure gp is NULL or points to valid data	Sean Anderson	1	-3/+25
2020-09-30	riscv: Consolidate fences into AMOs for available_harts_lock	Sean Anderson	1	-6/+3
2020-09-30	Revert "riscv: Clear pending interrupts before enabling IPIs"	Sean Anderson	1	-2/+0
2020-07-24	riscv: Fix linking error when building u-boot-spl with no SMP support	Leo Yu-Chi Liang	1	-0/+2
2020-07-01	riscv: Clear pending interrupts before enabling IPIs	Sean Anderson	1	-0/+2
2020-04-23	riscv: Provide a mechanism to fix DT for reserved memory	Atish Patra	1	-0/+1
2020-04-23	riscv: Introduce SPL_SMP Kconfig option for U-Boot SPL	Bin Meng	1	-7/+7
2020-04-23	riscv: Merge unnecessary SMP ifdefs in start.S	Bin Meng	1	-4/+0
2020-02-10	riscv: Remove unnecessary instruction	Sean Anderson	1	-3/+2
2020-01-17	common: Move relocate_code() to init.h	Simon Glass	1	-1/+1
2019-12-10	riscv: add option to wait for ack from secondary harts in smp functions	Lukas Auer	1	-0/+2
2019-12-10	riscv: Fix clear bss loop in the start-up code	Rick Chen	1	-2/+2
2019-09-03	riscv: update fix_rela_dyn	Marcus Comstedt	1	-5/+5
2019-08-26	riscv: support SPL stack and global data relocation	Lukas Auer	1	-1/+34
2019-08-26	riscv: add SPL support	Lukas Auer	1	-1/+22
2019-08-26	riscv: add run mode configuration for SPL	Lukas Auer	1	-3/+3
2019-08-15	riscv: Access CSRs using CSR numbers	Bin Meng	1	-2/+1
2019-05-09	riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is ena...	Rick Chen	1	-0/+2
2019-05-09	riscv: Introduce CONFIG_XIP to support booting from flash	Rick Chen	1	-0/+6
2019-04-08	riscv: hang if relocation of secondary harts fails	Lukas Auer	1	-1/+12
2019-04-08	riscv: do not rely on hart ID passed by previous boot stage	Lukas Auer	1	-0/+4
2019-04-08	riscv: add support for multi-hart systems	Lukas Auer	1	-1/+133
2019-04-08	riscv: save hart ID in register tp instead of s0	Lukas Auer	1	-2/+2
2019-04-08	riscv: delay initialization of caches and debug UART	Lukas Auer	1	-8/+8
2018-12-18	riscv: Save boot hart id to the global data	Bin Meng	1	-0/+4
2018-12-18	riscv: Move trap handler codes to mtrap.S	Bin Meng	1	-89/+0
2018-12-05	riscv: ax25-ae350: Pass dtb address to u-boot with a1 register	Rick Chen	1	-2/+0
2018-12-05	riscv: Add kconfig option to run U-Boot in S-mode	Anup Patel	1	-8/+15
2018-11-26	riscv: cache: Implement i/dcache [status, enable, disable]	Rick Chen	1	-0/+6
2018-11-26	riscv: save hart ID and device tree passed by prior boot stage	Lukas Auer	1	-2/+10
2018-11-26	riscv: do not blindly modify the mstatus CSR	Lukas Auer	1	-4/+4
2018-11-26	riscv: remove unused labels in start.S	Lukas Auer	1	-9/+0
2018-11-26	Drop CONFIG_INIT_CRITICAL	Bin Meng	1	-13/+0
2018-11-26	riscv: align mtvec on a 4-byte boundary	Lukas Auer	1	-1/+1