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path: root/arch/riscv/dts
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2023-11-29riscv: dts: Add StarFive VisionFive 2 board device treeHal Feng4-113/+493
2023-11-29riscv: dts: jh7110: Add a new clock input to gmacHal Feng1-4/+8
2023-09-11riscv: dts: Add link state register to PCIe syscon nodes.Kevin.xie1-2/+2
2023-09-05dts: usb: Add starfive,usb2-only to zeroMinda Chen1-0/+1
2023-08-25dts: usb: Add USB 3.0 clock dts.Minda Chen1-0/+15
2023-08-25dts: starfive: devkits: Update usb device tree nodeYanhong Wang1-4/+8
2023-07-28riscv: dts: starfive: limit cclk_in frequencyWilliam Qiu1-0/+2
2023-07-18riscv: dts: starfive: jh7110: replace mipi&hdmi nodeKeith Zhao1-4/+4
2023-05-18riscv: dts: starfive: add zicsr_zifencei to riscv,isa stringAndy Hu1-6/+6
2023-04-10dts: pmu: remove pmu dts stall cycles config.Minda Chen1-5/+2
2023-04-04riscv: dts: jh7110: Add L2 pretcher configurationSamin Guo1-0/+10
2023-03-28riscv: dts: starfive: Add gpio-controller for the gpio nodeHal Feng1-0/+2
2023-03-08riscv: dts: enable hdmi dts config in ubootkeith.zhao2-46/+13
2023-02-22riscv: dts: starfive: Enable PCIe host controllerMason Huo2-12/+114
2023-02-17dts:riscv:jh7110: add mipi driver nodekeith.zhao2-94/+329
2023-02-03exclude opensbi memory range in device treeFelix Moessbauer1-1/+11
2023-01-09dts: add boot-hart-id property in dtsminda.chen1-0/+1
2023-01-06Merge branch 'CR_3049_Hibernation_mason.huo' into 'jh7110-master'andy.hu2-0/+20
2023-01-06Merge branch 'CR_2708_VOUTCLK_yanhong.wang' into 'jh7110-master'andy.hu1-1/+0
2023-01-05clk:starfive: Add vout clock driver for StarFive JH7110Yanhong Wang1-1/+0
2023-01-05dts: add i2c5 and attach pmic configurationminda.chen2-0/+20
2023-01-03dts: pmu : add riscv pmu dts configminda.chen1-0/+46
2022-11-23dts:starfive:Add pinctrl configJianlong Huang2-7/+59
2022-11-01dts:starfive:jh7110: set gmac phy tx_inverted for JH7110A/B.Samin Guo1-1/+11
2022-10-18riscv: dts: jh7110: Add reset property to DDR control nodeYan Hong Wang1-1/+5
2022-10-18riscv:dts:starfive-jh7110: modify Model and riscv,isa infoyanhong.wang2-6/+6
2022-10-18board:starfive:evb: update uart3-uart5 resetsyanhong.wang1-6/+12
2022-10-18clk:starfive-jh7110: Update pll0/pll1/pll2 clkyanhong.wang1-18/+0
2022-10-18riscv:dts:starfive-jh7110: Modify sd node configurationyanhong.wang4-38/+7
2022-10-18SPL:riscv:starfive-jh7110: Adjust CPU working frequencyyanhong.wang1-1/+1
2022-10-18riscv:dts:starfive-jh7110: add ethernet-phy delay_chain configyanhong.wang2-4/+17
2022-10-18riscv:dts:starfive-jh7110: add ddr device nodeyanhong.wang1-0/+7
2022-10-18clk:starfive-jh7110: Update pll0/pll1/pll2 clkyanhong.wang2-3/+22
2022-10-18board:starfive: add starfive evb board supportyanhong.wang4-0/+149
2022-10-18riscv:dts: update clk&reset propertiesyanhong.wang2-157/+443
2022-10-18riscv:dts: update clk&reset propertiesyanhong.wang2-53/+182
2022-10-18riscv:dts: add jh7110 supportyanhong.wang6-0/+1341
2021-07-21board: sifive: drop stuff related to unmatched revision 1Zong Li4-1501/+1
2021-07-07riscv: dts: add OpenPiton RISC-V board dts supportTianrui Wei1-2/+2
2021-07-06riscv: dts: add dts for unmatched rev1Zong Li4-1/+1501
2021-07-06riscv: sifive: fu740: Support i2c in splZong Li1-0/+4
2021-07-06board: riscv: add openpiton-riscv64 SoC supportTianrui Wei2-0/+154
2021-06-28Merge tag 'v2021.07-rc5' into nextTom Rini3-7/+61
2021-06-17k210: dts: Set PLL1 to the same rate as PLL0Sean Anderson1-0/+2
2021-06-17riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL configBin Meng3-0/+54
2021-06-17riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bitBin Meng1-1/+1
2021-06-17riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodesBin Meng2-4/+0
2021-06-17riscv: ae350: dts: Remove the unnecessary space in bootargsBin Meng2-2/+2
2021-06-17riscv: ae350: dts: Add SPDX license headerBin Meng2-0/+4
2021-05-31riscv: dts: add SiFive Unmatched board supportGreen Wan4-0/+1790